Storage apparatus and input/output control method for the storage apparatus

ABSTRACT

An I/O control apparatus comprises a temporary memory circuit divisible into a plurality of segments according to the type of an I/O request for temporarily storing data to and from an external system, and a notification means for notifying the external system of the amount of the data that can be transferred continuously between the external system and the temporary memory circuit in response to a data transfer amount request from the external system.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a division of application Ser. No.09/020,929, filed Feb. 9, 1998 entitled Recording-Reproducing Apparatusand Input/Output Control Method for the Recording-Reproducing Apparatus,which is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a storage apparatus such as amagnetic disk apparatus etc. and in particular to a storage apparatusfor recording and reproducing real-time data such as a image data bycontrolling a temporary memory circuit built into the storage apparatusand an input/output (I/O) control method for such a storage apparatus.

[0003] In recent years, the recording density and the data transfer ratein storage apparatus, such as magnetic disk apparatus, have been ever onthe increase. These disk apparatuses are used also for recording andreproducing multi-channel image data.

[0004] For image data to be continuously recorded or reproduced at apredetermined rate in a disk apparatus, it is necessary to process anI/O request within a predetermined time in the disk apparatus.Processing a plurality of I/O requests requires accurate time managementof each I/O request.

[0005] The time management of the I/O requests can be executed bysoftware processing of a host computer for controlling the diskapparatus. Managing I/O requests in real time, however, produces theproblem of a heavy load imposed on the CPU. In view of this, asdisclosed in unexamined Japanese publication Hei 8-171526, a dedicatedinterface unit is connected between the disk apparatus and the hostcomputer for time management of I/O requests.

[0006] Further, in recording or reproducing multi-channel image data, atemporary memory unit is required to buffer data that would otherwise belost due to the suspension of data transfer mechanical operations suchas the disk apparatus seek operation.

[0007] Conventional disk apparatuses, as disclosed in U.S. Pat. No.5,465,343, for example, comprise a temporary memory circuit forimproving the storage performance, in which a temporary memory circuitis used as a buffer memory or a cache memory. The temporary memorycircuit is used also for prefetching. The prefetching is a process forreading a succeeding data after reading data corresponding to an outputrequest, and storing the succeeding data in the temporary memory unitwith the aim of improving the performance of processing sequential dataI/O requests.

[0008] The conventional storage apparatus using the above-mentionedinterface unit and disk apparatus will now be explained with referenceto the accompanying drawings.

[0009]FIG. 39 is a block diagram showing a general system configurationof the storage apparatus using the above-mentioned interface unit andthe conventional disk apparatus. As shown in FIG. 39, a host computer71, a reference clock generating section 72 and an interface unit 73 areconnected to an I/O bus 75. A disk apparatus 74 is connected to theinterface unit 73 through a data bus 76.

[0010] The interface unit 73 includes a bus interface control section 82(hereinafter called “the bus I/F control section 82”), an I/O controlsection 84, a schedule management section 81 and a queue-with-prioritymanagement section 83. In the interface unit 73, the schedule managementsection 81 controls the sequence of execution of I/O requests.

[0011] The host computer 71 issues a data I/O request to the interfaceunit 73. The I/O request is received through the I/O bus 75 by the I/Fcontrol section 82 of the interface unit 73, and stored in thequeue-with-priority management section 83 through a command bus 73. Thequeue-with-priority management section 83 manages a queue with priority,a pending queue and an I/O execution queue.

[0012] The reference clock information generated in the reference clockgenerating section 72 passes on the I/O bus 75, and is stored in theschedule management section 81 through the bus I/F control section 82.

[0013] The schedule management section 81 transfers an I/O request tothe queue with priority in the queue-with-priority management section83. Upon receipt of the request, the schedule management section 81determines whether the queue with priority contains an I/O request.

[0014] In the case where the queue with priority contains an I/Orequest, the schedule management section 81 fetches the particular I/Orequest and determines whether the request has a high order of prioritywith a specified processing time. In the case where the request has ahigh priority, the schedule management section 81 transfers theparticular I/O request to the I/O control section 84, while in the casewhere the priority of the request is low, the schedule managementsection 81 adds the request to the pending queue.

[0015] In the case where no I/O request is contained in the queue withpriority, in contrast, the pending queue is checked. In the presence ofany I/O request contained in the pending queue, the particular I/Orequest is fetched and, when it is before the lapse of a set processingtime, the fetched I/O request is executed. In the case where the I/Orequest has passed the set processing time and has timed out, on theother hand, the request is discarded or returned to the pending queue.

[0016] The I/O control section 84 controls the disk apparatus 74,accesses an instruction on data I/O, and executes the data write or readoperation.

[0017]FIG. 40 is a diagram showing a method for dividing and controllingthe buffer memory making up the temporary memory unit of the diskapparatus 314.

[0018] A portion (a) in FIG. 40 shows an adaptive segmentation method.As shown in the portion (a) of FIG. 40, the buffer memory is dividedinto a plurality of segments which can be assigned to a write buffer anda cache for read data. Also, each segment size can be changed inaccordance with the data size to be transferred in response to awrite/read command.

[0019] A portion (b) in FIG. 40 shows a fixed segmentation method. Inresponse to a set command from an external system, the buffer memory canbe divided into a plurality of segments of fixed size. With the diskapparatus conforming to the SCSI-3 (SCSI: Small Computer SystemInterface) specification, for example, the number of segments and thesize of each segment of the buffer memory can be set appropriately. Eachsegment size is identical and fixed.

[0020] In the above-mentioned conventional control method, the diskapparatus 74 uses the buffer memory divided into segments. As a result,the conventional storage apparatus meets the multi-task requirement inthe recording and reproduction of multi-channel image data, and improvesstorage performance.

[0021] Explanation will be made below about certain problems encounteredin the conventional storage apparatus configured as described above.

[0022] A first problem of the conventional storage apparatus lies in themanagement of the execution time of an I/O request.

[0023] The time for executing an I/O request in the disk apparatus ofthe conventional storage apparatus is sometimes considerably variabledepending on the variations in the time for access to a target area,i.e., the seek time or the waiting time for rotation and the operatingconditions of the temporary memory circuit. In the conventional storageapparatus having the above-mentioned configuration, the interface unitand the external system lack means for obtaining information on the timefor accessing the disk apparatus and the operating conditions of thetemporary memory circuit, and therefore the execution time cannot beaccurately predicted. As a result, a time management assuming anexcessively long execution time is required for meeting a time limit toensure that data is not lost, thereby leading to the problem of adeteriorated processing efficiency.

[0024] A second problem of the conventional storage apparatus is thatthe response to an I/O request is occasionally delayed because ofdeteriorated performance.

[0025] In the conventional storage apparatus, an I/O request withhigh-priority having a time limit is executed preferentially, while anI/O request low in priority is set in pending. In this way, the imagedata having high-priority are continuously recorded and reproduced. Inthe case where a high-priority I/O request is not contained in the queuebut only low-priority I/O requests are pending, the I/O requests of lowpriority are executed unconditionally.

[0026] Consequently, even in the case where a high-priority I/O requestis applied from an external system such as a host computer during theexecution of a low-priority I/O request, the high-priority I/O requestcannot be executed before complete execution of the low-priority I/Orequest. In such a case, the external system is not informed of thereason that the high-priority I/O request therefrom is not executedimmediately and is required to wait until complete execution of thelow-priority I/O request.

[0027] In other words, in the conventional storage apparatus, the timemanagement does not take the execution time of I/O requests intoconsideration. As a result, when a high-priority I/O request is input,the high-priority I/O request is sometimes required to wait forexecution.

[0028] Assume, on the other hand, that an I/O request of an image highin priority with a time limit for execution is input in the presence ofan I/O request for random data, low in priority, without any time limitfor waiting in queue. In such a case, the I/O request for an image isexecuted in priority even in the case where a time margin exists,sometimes considerably delaying the response to the I/O request for therandom data.

[0029] Still another problem of the conventional disk apparatuses isthat of inefficient use of the temporary memory circuit.

[0030] For continuous recording and reproduction to be assured in thedisk apparatus for the image data, high in transfer rate, a number oftemporary memory circuits are required. Image data or program data lowin transfer rate, however, can be processed in a smaller number ofmemory circuits. Generally, the image data are continuous andsequential, while the program data are discrete. The method ofcontrolling the buffer memory/cache memory varies depending onproperties of the data.

[0031] The method of using the temporary memory circuit for theconventional disk apparatus is configured to meet the requirements ofarbitrary data. The conventional method, however, is not suitable forassuring continuous recording and reproduction, or improving the storageperformance of image data. In the case of repeat play of image data, forexample, a wasteful prefetch operation occurs, and thereby the responseis sometimes delayed and the performance is deteriorated.

[0032] In recording or reproducing multi-channel data containing imagedata, the size and the control method of the temporary memory circuit isrequired to be determined in accordance with the transfer rate, thereal-time requirement, the continuity, etc. of each channel.Nevertheless, the conventional disk apparatus, of which the buffermemory can be divided into a plurality of segments or of which thesegment size can be changed, cannot set the multi-channel data tocorrespond with each segment, for each channel, and therefore cannot setthe segment size and the control method for each channel in accordancewith different transfer rates, the real-time requirement or thecontinuity.

SUMMARY OF THE INVENTION

[0033] An object of the present invention is to provide a storageapparatus which, in order to solve the problem of delay in processing anI/O request, predicts the execution time of each I/O request from anexternal system and thereby assures an accurate processing of the I/Orequest. Another object of the present invention is to provide a storageapparatus and an I/O control method which can assure an accuratecontinuous recording and reproduction of image data or other data ofhigh priority and which can efficiently process I/O requests of lowpriority. Still another object of the present invention is to provide astorage apparatus which can selectively execute an I/O request forrandom data, low in priority, which has a time limit for processing.

[0034] In order to achieve the above-mentioned objects, according to oneaspect of the present invention, there is provided a storage apparatuscomprising input means supplied with a request for predicting the I/Oexecution time from an external system, and a determining means forpredicting the execution time of an I/O request in response to therequest for the I/O execution time prediction.

[0035] With the above-mentioned configuration, the storage apparatusaccording to the present invention can correctly predict the executiontime in response to an I/O request and can secure the execution time forthe I/O request in response to an external system.

[0036] According to another aspect of the present invention, there isprovided a storage apparatus comprising determining means for predictingthe execution time in response to an I/O request from an external systemand determining whether the predicted execution time can be realizedwithin a time limit set by the external system, and an I/O requestprocessing means for executing the I/O request in the case where the I/Orequest is determined to be executable by the determining means and forterminating the processing in the case where the I/O request isdetermined as not to be executable, thereby giving a response to theexternal system based on the result of the determination.

[0037] According to still another aspect of the invention, there isprovided a storage apparatus further comprising determining means forgiving a response to an I/O data transfer amount request from theexternal system including a data size for which the storage apparatus iscapable of transferring within a time limit preset by the externalsystem.

[0038] With the above-mentioned configuration, the storage apparatusaccording to the present invention can predict and respond to a datasize capable of being input or output within a time limit, so that theapparatus can assure the execution time for a high-priority requestwhile providing a maximum transfer rate for a low-priority request,thereby improving the processing efficiency. Also, the storage apparatusaccording to the present invention permits an external system such as ahost computer to determine whether or not an I/O request can be executedwithin a time limit, and therefore can assure the execution completiontime for each data I/O operation and can thus easily execute thereal-time management of I/O requests.

[0039] According to a further aspect of the present invention, there isprovided a storage apparatus comprising a temporary memory circuitcapable of being divided into a plurality of segments according to thetype of I/O request, wherein the determining means gives an availablesize of a corresponding segment as a writable data size in response to awrite size request from an external system.

[0040] According to a still further aspect of the present invention,there is provided a storage apparatus comprising a temporary memorycircuit capable of being divided into a plurality of segments inaccordance with the type of I/O request, and a preread means for readingdata from a designated area of a recording medium and storing the datatemporarily in a corresponding segment, wherein an available size of acorresponding segment is offered as a data size capable of being prereadin response to a preread size request, and a preread data size of acorresponding segment is offered as a readable data size in response toa read size request.

[0041] With the above-mentioned configuration, the storage apparatusaccording to the present invention offers an available size of acorresponding segment in response to a write data transfer amountrequest, offers a preread data size in response to a read data transferamount request, and offers an available size of a corresponding segmentin response to a preread data transfer amount request, wherein the I/Odata can always be transferred in bursts and the time management of I/Orequests can be accurately facilitated. Also, the present invention hasthe effect of shortening the time during which an I/O bus is occupied.

[0042] According to a yet further aspect of the present invention, thereis provided an I/O control method for a storage apparatus comprisingnotification means for notifying the continuously-transferable amount ofdata to an external system in response to a data transfer amount requestfrom the external system, in which a method of data transfer between theexternal system and the storage apparatus is selected in accordance withthe transferable data amount. With this configuration, the I/O controlmethod according to the present invention can always continuouslytransfer the I/O data.

[0043] According to still another aspect of the present invention, thereis provided a storage apparatus, which identifies the type of I/Orequests accumulated, and in the case where an I/O request is one with atime limit, the apparatus executes a type of an I/O request selectivelyin accordance with the time length remaining before a deadline which iscalculated based on the time limit.

[0044] According to a further aspect of the present invention, there isprovided a storage apparatus which calculates the time remaining beforea deadline based on the time limit for accumulated I/O requests andselects the I/O request with the minimum remaining time among theaccumulated I/O requests. In the case where the remaining time of thedata request is smaller than a predetermined value, the apparatusexecutes the particular I/O request while in the case where theabove-mentioned condition fails to be met, the apparatus executes theaccumulated I/O requests by selecting the sequence of execution inaccordance with a data recording position corresponding to each I/Orequest.

[0045] With the above-mentioned configuration, the storage apparatusaccording to the present invention, in which an I/O request is selectedfor execution based on the time remaining before a deadline, theapparatus can first assure the continuous recording and reproduction ofimage data or the like and then can assign the processing time to therecording and reproduction of random data, thereby improving the storageperformance.

[0046] Another object of the present invention is to provide a storageapparatus for recording and reproducing image data by a method ofcontrolling a temporary memory circuit suitable for image data in orderto solve the above-mentioned problem of efficient use of the temporarymemory circuit. Still another object of the present invention is toprovide a storage apparatus in which a temporary memory circuit can bedivided into a plurality of segments in accordance with a requirednumber of channels, and in which the size and the method of controllingthe temporary memory circuit can be set in accordance with a transferrate and a real-time processing requirement of each channel.

[0047] In order to achieve the above-mentioned objects, according to oneaspect of the present invention, there is provided a storage apparatuscomprising a management information memory means for storing the filemanagement information corresponding to the data recorded in a recordingmedium, wherein the management information is reproduced in response toan auto read request from an external system, and wherein the positionon the recording medium where the location of a data block to betransferred to the external system is stored is determined, and the datablock is preread.

[0048] According to another aspect of the present invention, there isprovided a storage apparatus comprising a preread means for reproducingdata blocks from a recording medium in response to a plurality ofpreread requests having an identifier from external system andtransferring the data blocks to a temporary memory circuit, wherein inthe case where an I/O request with an identifier is received from anexternal system, a data block is selected from among those preread inaccordance with the identifier and transferred to the external system.

[0049] According to still another aspect of the present invention, thereis provided a storage apparatus, in which the type of accumulated writedata requests is identified and the data amount to be recordedcontinuously in a recording medium is selected and recorded, and inwhich the number of requests to be accumulated is selected byidentifying the types of the accumulated read data requests therebyreproducing the data continuously from the recording medium inaccordance with the number of the accumulated requests.

[0050] According to yet another aspect of the present invention, thereis provided a storage apparatus comprising a prefetch means fortransferring the data reproduced from a recording medium to a temporarymemory circuit, wherein the type of each I/O request from the externalsystem is identified, and one of a plurality of prefetch methods havingdifferent data amounts to be prefetched and different time lengthsrequired for the prefetch processing is selected and executed inaccordance with the type of a particular I/O request.

[0051] With this configuration, the storage apparatus according to thepresent invention can realize a method of controlling the temporarymemory circuit suitable for transfer of image data, and a significanteffect of an improved performance is attained as a result of a reducedload of transfer processing of the external system and an improvedefficiency of the data recording and reproducing operation of thestorage apparatus.

[0052] In order to achieve the above-mentioned objects, according to oneaspect of the present invention, there is provided a storage apparatuscomprising a temporary memory circuit divisible into a plurality ofsegments, and a temporary memory circuit control means for selecting asegment based on the information for identifying the write/read requestfrom an external system and causing the write/read data to betemporarily stored in the selected segment.

[0053] According to another aspect of the present invention, there isprovided a storage apparatus comprising a temporary memory circuitdivisible into a plurality of segments, and a temporary memory circuitcontrol means for determining a segment size, a method of data transferfrom an external system and a method of data transfer to a recordingmedium for each segment based on the setting information supplied fromthe external system, selecting a segment based on the information foridentifying the write/read request from the external system, andcontrolling the data transfer from the external system and the datatransfer to the recording medium by the transfer method thus determined.

[0054] According to still another aspect of the present invention, thereis provided a storage apparatus wherein the conditions for starting andstopping the data transfer between an external system and acorresponding segment, the conditions for starting and stopping the datatransfer to and from the recording medium, the order of priority of datatransfer to and from the recording medium and the unit of access fromthe external system, are determined on the basis of the settinginformation supplied from the external system.

[0055] According to yet another aspect of the present invention, thereis provided a storage apparatus, wherein a recording/reproducing areafor writing a data of a corresponding segment in a recording medium orfor reading a data stored in a corresponding segment from a recordingmedium is set on the basis of the setting information supplied from theexternal system.

[0056] With this configuration of the storage apparatus according to thepresent invention, a data size and a transfer method are set for eachsegment based on the setting information from the external system, andthe data transfer from and to the external system and from and to therecording medium are controlled by the transfer method thus set, makingit possible to set different memory sizes and different control methodscorresponding to different transfer rates, image data having real-timeprocessing requirement, or the requirement of data other than the imagedata.

[0057] According to a further aspect of the present invention, there isprovided a storage apparatus, wherein the unit of access to the segmentsfrom an external system is set by the setting information from anexternal system thereby to permit the external system to access thesegments with smaller than a normal access unit for an improved randomaccess efficiency.

[0058] According to a still further aspect of the present invention,there is provided a storage apparatus, wherein different storage areasare set for different segments based on the setting information suppliedfrom an external system, and in this way one-to-one correspondence canbe established between the storage areas and the segments, therebyguaranteeing the identity between the data in each segment and the dataon the disk.

[0059] While the novel features of the invention are set forthparticularly in the appended claims, the invention, both as toorganization and content, will be better understood and appreciated,along with other objects and features thereof, from the followingdetailed description taken in conjunction with the drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0060]FIG. 1 is a block diagram showing a configuration of a diskapparatus according to a first embodiment of the invention;

[0061]FIG. 2 is a flowchart showing the flow of processing an I/Ocommand according to the first embodiment;

[0062]FIG. 3 is a flowchart showing the flow of processing an executiontime prediction command according to the first embodiment;

[0063]FIG. 4 is a flowchart showing the flow of the process forpredicting the execution time of a write command according to the firstembodiment;

[0064]FIG. 5 is a diagram showing various parameters of a buffer RAMaccording to the first embodiment;

[0065]FIG. 6 is a graph showing an example of the accumulated segmentamount, the remaining data amount and the untransferred data amountaccording to the first embodiment;

[0066]FIG. 7 is a flowchart showing the flow of the process forpredicting the execution time of a read command according to the firstembodiment;

[0067]FIG. 8 is a flowchart showing the flow of processing a transferdata amount request command according to a second embodiment;

[0068]FIG. 9 is a flowchart showing the flow of the process forpredicting a writable data size according to the second embodiment;

[0069]FIG. 10 is a flowchart showing the flow of the process forpredicting a readable data size according to the second embodiment;

[0070]FIG. 11 is a flowchart showing the flow of processing a transferdata amount request command according to a third embodiment;

[0071]FIG. 12 is a block diagram showing a general configuration of avideo processing unit according to a fourth embodiment;

[0072]FIG. 13 is a diagram for explaining a method of segmenting theareas of the buffer RAM according to the fourth embodiment;

[0073]FIG. 14 is a flowchart showing the flow of operation of the videoprocessing unit according to the fourth embodiment;

[0074]FIG. 15 is a flowchart for explaining the flow of the recordingoperation of a storage apparatus according to the fourth embodiment;

[0075]FIG. 16 is a diagram for explaining a preread data managementtable according to the fourth embodiment;

[0076]FIG. 17 is a flowchart for explaining the reproducing operation ofa storage apparatus according to the fourth embodiment;

[0077]FIG. 18 is a flowchart for explaining the data retrieval operationof a storage apparatus according to the fourth embodiment;

[0078]FIG. 19 is a diagram for explaining the file managementinformation according to the fourth embodiment;

[0079]FIG. 20 is a flowchart for explaining the auto read operation of astorage apparatus according to the fourth embodiment;

[0080]FIG. 21 is a flowchart for explaining the recording operation of astorage apparatus according to a fifth embodiment;

[0081]FIG. 22 is a flowchart for explaining the reproducing operation ofa storage apparatus according to the fifth embodiment;

[0082]FIG. 23 is a flowchart for explaining the prefetch operation of astorage apparatus according to the fifth embodiment;

[0083]FIG. 24 is a flowchart for explaining the recording andreproducing operation of a storage apparatus according to a sixthembodiment;

[0084]FIG. 25 is a diagram for explaining a request accumulation queueaccording to the sixth embodiment of the invention;

[0085]FIG. 26 is a block diagram showing a configuration of a diskapparatus according to a seventh embodiment of the invention;

[0086]FIG. 27 is a block diagram showing a configuration of a HDDcontrol circuit according to the seventh embodiment;

[0087]FIG. 28 is a diagram showing the correspondence between thesegment setting register of a buffer control circuit and each segment ofa buffer RAM;

[0088]FIG. 29 is a flowchart showing the operation of processing asegment setting command in the disk apparatus according to the seventhembodiment;

[0089]FIG. 30 is a diagram showing an example of changing a segmentsetting in response to a segment setting command according to theseventh embodiment;

[0090]FIG. 31 is a diagram showing various parameters associated withthe segment accumulation, the host transfer (meaning data transfer to orfrom the host) and the disk transfer (meaning data transfer to or fromthe disk) according to the seventh embodiment;

[0091]FIG. 32 is a flowchart showing the process of data transfer froman external system such as a host to a segment according to the seventhembodiment;

[0092]FIG. 33 is a flowchart showing the host transfer process from asegment to a disk according to the seventh embodiment;

[0093]FIG. 34 is a flowchart showing the host transfer process from adisk to another segment according to the seventh embodiment;

[0094]FIG. 35 is a flowchart showing the host transfer process from asegment to an external system according to the seventh embodiment;

[0095]FIG. 36 is a flowchart of processing a transfer rate settingcommand according to an eighth embodiment;

[0096]FIG. 37 is a diagram showing the correspondence between thesegmentation of the buffer RAM and the segment setting registeraccording to a ninth embodiment;

[0097]FIG. 38 is a diagram showing the correspondence between thesegment setting register of the buffer control circuit, the segmentationof the buffer RAM and each area on the disk according to a tenthembodiment;

[0098]FIG. 39 is the block diagram showing a system configuration of aconventional storage apparatus; and

[0099]FIG. 40 is the diagram showing the method of controlling thesegmentation of the buffer memory of the conventional disk apparatusconstituting a storage apparatus.

[0100] It will be recognized that some or all of the figures areschematic representations for purposes of illustration and do notnecessarily depict the actual relative sizes or locations of theelements shown.

DETAILED DESCRIPTION OF THE INVENTION

[0101] A disk apparatus of a storage apparatus according to preferredembodiments of the present invention will be explained below withreference to the accompanying drawings.

[0102] <<Embodiment 1>>

[0103]FIG. 1 is a block diagram showing a configuration of a diskapparatus according to a first embodiment.

[0104] In FIG. 1, a disk apparatus is connected to an external system(not shown) such as a host computer through an I/O bus. Data arereceived and transmitted between the disk apparatus and the externalsystem by an interface circuit 2. As shown in FIG. 1, in addition to theinterface circuit 2, the disk apparatus according to the firstembodiment comprises a buffer RAM 3 which is a temporary memory circuitfor temporarily storing data, a read/write signal processing circuit 4for encoding and decoding the data, a head-disk assembly 5, an actuatordrive circuit 8 and a HDD control circuit 9. The RAM is an abbreviationof a random access memory, and HDD an abbreviation of a hard disk drive.

[0105] The head-disk assembly 5 includes a disk 1, a head assembly 6 andan actuator 7. The actuator 7 is driven by an actuator drive circuit 8.The HDD control circuit 9 is for controlling the buffer RAM 3, theread/write signal processing circuit 4 and the actuator drive circuit 8based on various commands supplied from the external system.

[0106] The interface circuit 2 issues data and commands, received fromthe external system. The interface circuit 2 also outputs data receivedfrom the buffer RAM 3 and the command response from the HDD controlcircuit 9 to the external system.

[0107] The read/write signal processing circuit 4 encodes write datafrom the buffer RAM 3 and outputs the write data as a write signal to ahead 6 a. Also, the read/write signal processing circuit 4 decodes theread signal read by the head 6 a from a track of the disk 1 and outputsit as read data to the buffer RAM 3.

[0108] The HDD control circuit 9 receives a command from the externalsystem through the interface circuit 2 and interprets the command. TheHDD control circuit 9 that interprets the command, controls the bufferRAM 3, the read/write signal processing circuit 4 and the actuator drivecircuit 8 thereby to perform the data write and read operation. Also,when the command requests a response, the HDD control circuit 9transmits a command response to the external system through theinterface circuit 2.

[0109] The actuator drive circuit 8 outputs a drive signal to theactuator 7 based on an actuator control signal from the HDD controlcircuit 9. The actuator drive circuit 8 controls the operation of theactuator 7 and positions the head 6 a through movement of the headassembly 6.

[0110] [Operation of HDD Control Circuit]

[0111] The operation of the HDD control circuit 9 of the disk apparatusaccording to the first embodiment configured as described above will beexplained with reference to FIGS. 2 and 3.

[0112]FIG. 2 is a flowchart showing the operation for processing the I/Ocommand by the HDD control circuit 9 according to the first embodiment.

[0113] In FIG. 2, upon application of an I/O command from the externalsystem to the HDD control circuit 9 through the interface circuit 2(step S1), the HDD control circuit 9 determines whether the applied I/Ocommand is one requiring the prediction of the execution time or not(step S2).

[0114] In the case where the applied I/O command is one requiring theprediction of the execution time (execution time prediction command),the execution time of the I/O command is predicted according to: (1) theparameters of the I/O operation delivered as command parameters, and (2)the internal state of the HDD (step S3). Then, the predicted executiontime is compared with a deadline providing a maximum tolerable executiontime delivered as a command parameter (step S4). When the execution timeis not longer than the deadline, the data I/O is executed (step S5).When the execution time is longer than the deadline, the I/O is notexecuted, and the result is transmitted to the external system as anerror termination process (step S6).

[0115] In the case where step S2 determines that the applied I/O commandis not the one requiring prediction of the execution time, the data I/Ooperation is immediately executed {step S5).

[0116]FIG. 3 is a flowchart showing the operation for processing theexecution time prediction command by the HDD control circuit 9 accordingto the first embodiment.

[0117] In FIG. 3, upon application of an execution time predictioncommand from the external system to the HDD control circuit 9 (stepS11), the HDD control circuit 9 predicts the execution time of the I/Ocommand according to: (1) the parameters delivered thereto as commandparameters for I/O operation and (2) the internal state of the HDD (stepS12). The execution time thus predicted is processed for notification ofthe external system.(step S13).

[0118] [Execution Time Prediction Process]

[0119] Now, the detailed operation of step S12 in the execution timeprediction process shown in FIG. 3 will be explained with reference toFIGS. 4 to 7.

[0120]FIG. 4 is a flowchart showing the flow of the process forpredicting the execution time of a write command, i.e, the time when thedata transfer to the buffer RAM 3 from the external system is completed.

[0121] As shown in FIG. 4, the HDD control circuit 9 first compares anavailable segment size with the size of the write data to be transferred(transfer data size) (step S21). In the case where the available segmentsize is larger than or equal to the size of the write data in step S21,the time when the continuous transfer would be terminated is calculatedfrom the I/O bus transfer rate and the transfer data size (step S27).

[0122] In the case where the transfer data size is larger than theavailable segment size, on the other hand, the occurrence ornon-occurrence of an overflow is determined (step S22).

[0123] In the case where no overflow occurs, the transfer terminationtime is calculated from the I/O bus transfer rate and the transfer datasize (step S27). In the case where an overflow occurs, on the otherhand, the size of the data not transferred as of the time of overflowoccurrence is calculated (step S23). Then, the period during which thetransfer is terminated is determined from the calculated size of thedata not yet transferred (step S24), and the situation is evaluatedaccording to the period during which the transfer is terminated (stepS25 or S26).

[0124] Now, each processing step of execution time prediction will beexplained in detail with reference to FIGS. 5 and 6.

[0125]FIG. 5 is a diagram showing various parameters of the buffer RAM 3according to the first embodiment. As shown in FIG. 5, according to thefirst embodiment, each parameter for the buffer RAM 3 is defined asfollows:

[0126] The transfer rate from the external system to the buffer RAM 3 isdefined as Vb (in units of MB/s), the write rate from the buffer RAM 3to the disk 1 is defined as Vd (in units of MB/s), the size of segmentsformed in buffer RAM 3 and assigned to the write command is defined asMb (in units of kB), and the write data size to be transferred isdefined as Mc (in units of kB).

[0127] Also, as a function of time t (in units of ms), the segmentaccumulation amount at time point t is defined as Ms(t) (in units ofkB), the amount of the data transferred to the segment from the externalsystem by a command at or before time point t and remaining in thesegment is defined as Md(t) (in units of kB), and the amount of the datato be transferred by a newly-issued command but not yet transferred asof the overflow time Tovf is defined as Mu (Tovf) (in units of kB).

[0128]FIG. 6 is a graph showing an example of the change with time ofthe segment accumulation amount Ms(t), the amount Md(t) of the remainingdata transferred by the previous command, and the amount of data Mu(t)not yet transferred by a newly-issued command as of time point t.

[0129] In the graph of FIG. 6, the parameters include Vb set to 16(MB/s), Vd set to 4 (MB/s), Mb set to 128 (kB), Mc set to 96 (kB), andMd (0) set to Ms (0) equal to 64 (kB). Also, an access period Tw1 due tothe previous command is set to 8 (ms), an access period Tw2 due to anewly-issued command is set to 12 (ms), a disk write period Td1 due tothe previous command is set to 16 (ms), and a disk write period Td2 dueto a newly-issued command is set to 24 (ms).

[0130] As shown in FIG. 6, the time period during which the transferreddata is finally written to the disk 1 is divided into below-mentionedfour time zones respectively having the periods T1, T2, T3, and T4 tocalculate the segment accumulation amount Ms(t), etc. T1 is determinedfrom:

0<T1 Tw1

[0131] The T1 period is the head seek and the rotational latency timedue to the previous command issued before a predicted time.

[0132] The access period Tw1 is calculated from the head position at thepredicted time point and a target head position, the speed profile athead seek time and the disk rotational speed. In the case where the headseek and the rotational latency are over, the access period Tw1=0. T2 isdetermined from:

Tw1<T2 Tw1+Td1

[0133] The T2 period represents the period during which the data iswritten in the disk in response to the command issued before thepredicted time point.

[0134] The disk write period Td1 is calculated from the data amount Md(0) remaining at the predicted time pint and the disk write speed Vdaccording to equation (1). T3 is determined from:

Td1=Md(0)/Vd   (1)

Tw1+Td1<T3 Tw1+Td1+Tw2

[0135] The T3 period represents the head seek and the rotational latencytime due to a new command to be issued.

[0136] The access period Tw2 is calculated from the head position as ofthe time point of T2 period termination, the target head position, thespeed profile at the head seek time and the disk rotational speed. T4 isdetermined from:

Tw1+Td1+Tw2<T4 Tw1+Td1+Tw2+Td2

[0137] The T4 period represents the period of time during which the datais written in the disk in response to a new command to be issued.

[0138] The disk write period Td2 is calculated from the data size Mc tobe transferred and the disk write speed Vd according to equation (2).

Td2=Mc/Vd   (2)

[0139] Now, each step of the execution time prediction process for thewrite command, shown in FIG. 4, will be described in detail.

[0140] Step S21: The Available Segment Size is Compared with theTransfer Data Size

[0141] The available segment size (Mb−Ms(0)) is compared with thetransfer data size Mc at the predicted time point.

[0142] Step S22: Determines Whether an Overflow has Occurred

[0143] In the case where the transfer data size is larger than theavailable segment size (Mb−Ms(0)<Mc), the segment is likely to overflowduring data transfer, and therefore the segment accumulation amount iscalculated to determine whether an overflow has occurred.

[0144] The remaining data amount Md(t) transferred by the previous I/Ocommand is given by the equation below.

[0145] T1 period:

Md(t)=Md(0)   (3)

[0146] T2 period:

Md(t)=Md(0)−Vd×(t−Tw1)   (4)

[0147] The data amount due to the previous command decreases accordingto this equation, while the write data is transferred to the buffer RAM3 from the external system, so that the segment accumulation amountMs(t) before occurrence of an overflow is given by the followingequation (6):

Ms (t)=Md(t)+Vb×t   (5)

[0148] In view of the fact that the segment accumulation amount Ms(t)exceeds the segment size Mb before continuous transfer of the dataamount Mc to the buffer RAM 3, the condition under which an overflowoccurs is given by the equation below. In the equation below, Tovfdesignates the time point of overflow, and Md(Tovf) the data amountremaining at the time point of overflow.

Md(Tovf)+Vb×Tovf=Mb and Tovf Mc/Vb   (6)

[0149] Equations (3) and (4) are substituted into Md(t) in equation (6)to determine the overflow time point Tovf and thereby determines whetheran overflow has occurred or not.

[0150] Step S23: Calculation of Transferred Data Size Not YetTransferred as of Time Point of Overflow.

[0151] The data size transferred to the buffer RAM 3 before occurrenceof an overflow is given as Vb×Tovf, and therefore the data size Mu(Tovf)not yet transferred as of the time of occurrence of an overflow is givenby equation (7).

Mu (Tovf)=Mc−Vb×Tovf   (7)

[0152] Step S24: Determination of Transfer Termination Period.

[0153] After overflow, data can be transferred to the buffer RAM 3 bythe amount written from the buffer RAM 3 to the disk 1. Therefore, thedata transfer is terminated at the time point when the data sizeMu(Tovf) not yet transferred as of the time of overflow is has beenwritten from the buffer RAM 3 into the disk 1.

[0154] In the case where a head seek or rotational latency occurs duringtransfer, the disk write operation is suspended and so is the transferto the buffer RAM 3. Consequently, the transfer is not completed duringthe head seek period T1 or the rotational latency period T3. Thetransfer thus is completed during T2 period or T4 period. Also, in thecase where the head seek or the rotational latency due to a new commanddoes not occur during the transfer, the transfer is completed during T2period. Otherwise, the transfer is completed during T4 period.

[0155] Whether the head seek and the rotational latency occurs due to anew command can be determined by comparing the amount of data Mu(Tovf)not yet transferred as of the time of overflow with the remaining amountof data Md(Tovf) due to the previous command.

[0156] Assume that the amount of data Mu(Tovf) not yet transferred issmaller than the remaining amount of data Md(Tovf) due to the previouscommand.

[0157] The data write operation due to the previous command continuesuntil the completion of the data transfer to the buffer RAM 3.Therefore, the transfer is not suspended by the head seek or therotational latency due to receiving a new command. In such a case, thecompletion time of the transfer of the data not yet transferred iscalculated in step S25.

[0158] Assume that the amount of data Mu(Tovf) not yet transferred isnot less than the remaining amount of data Md(Tovf) due to the previouscommand.

[0159] The data write operation due to the previous command is completedbefore the transfer to the buffer RAM 3 is completed. And the transferto the buffer RAM 3 is suspended by the head seek or the rotationallatency due to a new command. In such a case, the time of completetransfer of the data not yet transferred is calculated in step S26.

[0160] Step S25: Calculation of the Transfer Completion Time of the DataNot Yet Transferred (Transfer Completed During T2 Period)

[0161] In this case, the transfer is completed during T2 period, andtherefore the overflow occurs during the T1 or T2 period. Depending onthe time point of overflow occurrence, the transfer suspension perioddue to the head seek or rotational latency may be included in the periodof transfer of the data not yet transferred. The equation forcalculation of the transfer completion time Td, therefore, is differentfor different overflow time:

[0162] (1) In the case where overflow occurs during T1 period:

[0163] The transfer suspension period (Tw1−Tovf) is included in thetransfer period of the data not yet transferred. The transfer completiontime Td (in ms) is the sum of the time before overflow, the transfersuspension time and the time during which the data transferred beforethe overflow time point is written in the disk. This transfer completiontime Td is calculated from equation (8). $\begin{matrix}\begin{matrix}{{Td} = {{Tovf} + \left( {{Tw1} - {Tovf}} \right) + {\left( {{Mc} - {VbþTovf}} \right)/{Vd}}}} \\{= {{Tw1} + {\left( {{Mc} - {VbXTovf}} \right)/{Vd}}}}\end{matrix} & (8)\end{matrix}$

[0164] (2) In the case where an overflow occurs during T2 period:

[0165] The transfer suspension period is not included in the transferperiod of the data not yet transferred. The transfer completion time Tdis calculated from equation (9).

Td=Tovf+(Mc−Vb×Tovf)/Vd   (9)

[0166] Step S26: Calculation 2 of Transfer Completion Time of the DataNot Yet Transferred (Transfer Completed During T4 Period):

[0167] In this case, the transfer is completed during the T4 period, andtherefore it is possible that an overflow occurs in any of the T1 to T4periods.

[0168] (1) In the case where overflow occurs during T1 period:$\begin{matrix}\begin{matrix}{{Td} = {{Tovf} + \left( {{Tw1} - {Tovf}} \right) + {Tw2} + {\left( {{Mc} - {VbXþTovf}} \right)/{Vd}}}} \\{= {{Tw1} + {Tw2} + {\left( {{Mc} - {VbXTovf}} \right)/{Vd}}}}\end{matrix} & (10)\end{matrix}$

[0169] (2) In the case where overflow occurs during T2 period:

Td=Tovf+Tw2+(Mc−Vb×Tovf)/Vd   (11)

[0170] (3) In the case where overflow occurs during T3 period:$\begin{matrix}\begin{matrix}{{Td} = {{Tovf} + \left( {{Tw1} + {Td1} + {Tw2} - {Tovf}} \right) + {\left( {{Mc} - {VbXTovf}} \right)/{Vd}}}} \\{= {{Tw1} + {Td1} + {Tw2} + {\left( {{Mc} - {VbXTovf}} \right)/{Vd}}}}\end{matrix} & (12)\end{matrix}$

[0171] (4) In the case where overflow occurs during T4 period:

Td=Tovf+(Mc−Vb×Tovf)/Vd   (13)

[0172] Step S27: Calculation of Completion Time of Continuous Transfer

[0173] In the case where all the data can be continuously transferredfrom an external system to the buffer RAM 3, the transfer completiontime Td is calculated from equation (14).

Td=Mc/Vb   (14)

[0174] An example of determining a specific total execution time in eachstep of the execution time prediction process for the write commanddescribed above follows:

[0175] Step S21: Size of Vacant Segment at Predicted Time

(Mb−Ms (0))=64 (kB)

Transfer data size (Mc)=96 (kB)

[0176] Since Mb−Ms(0)<Mc, an overflow may occur.

[0177] Step S22: The Remaining Amount Md(t) of the Data Transferred tothe Segment in Response to the Previous Command is Calculated FromEquations (3) and (4).

0 t<8(T1 period): Md(t)=64(kB)

8 t<24(T2 period): Md(t)=64−Vd X (t−8 (kB)

[0178] From these equations and equation (6) concerning the conditionsfor overflow occurrence,

Md(Tovf)+16×Tovf=128 and Tovf×6

[0179] Substituting Md(t)=64 for T1 period into Md(Tovf) of thisequation determines Tovf=4. In the case where Md(t) for T2period=64−Vd×(t−8), there is no solution.

[0180] Step S23: The size of the data not yet transferred is given byequation (15)

Mc−Vb×Tovf=32   (15)

[0181] Step S24: The amount of data not yet transferred as of the timeof overflow is 32, and the remaining amount of the data due to thecommand previous to overflow is 64. Then the transfer is then completedduring the T2 period.

[0182] Step S25: The overflow occurs during the T1 period, and thereforethe transfer completion time Td of the data not yet transferred iscalculated from the below-mentioned equation (16): $\begin{matrix}\begin{matrix}{{Td} = {{Tw1} + {\left( {{Mc} - {Vbovf}} \right)/{Vd}}}} \\{= {{8 + {\left( {96 - {16 \times 4}} \right)/4}} = {16({ms})}}}\end{matrix} & (16)\end{matrix}$

[0183] The above-mentioned process calculates the execution time of awrite command, i.e., the transfer completion time. Also in combinationwith other parameters, the transfer completion time can be similarlydetermined.

[0184]FIG. 7 is a flowchart showing the flow of the process forpredicting the execution time of a read command, i.e., the completiontime of the data transfer from the buffer RAM 3.

[0185] As shown in FIG. 7, the HDD control circuit 9 first compares theamount of the preread data in the buffer RAM 3 with the amount of thetransferred data (step S31). In the first embodiment, the preread amountdata is defined as the amount of the data provisionally stored in thetemporary memory circuit.

[0186] In the case where the size of the preread data is larger than thesize of the transfer data in step S31, the transfer completion time forcontinuous transfer is calculated from the I/O bus transfer rate and thetransfer data size (step S37).

[0187] In the case where the transfer data size is larger than the sizeof the preread data in step S31, the occurrence or non-occurrence of anunderflow is determined (step S32).

[0188] In step S32, when the HDD control circuit 9 determines that therehas occurred no underflow, the completion time of a continuous transferis calculated from the I/O bus transfer rate and the transfer data size(step S37).

[0189] In the case where an underflow occurs, in contrast, the size ofthe data not yet transferred as of the time of the overflow iscalculated (step S33), and the period during which the transfer iscompleted is determined from the calculated size of the data not yettransferred (step S34). In step S34, the situation is evaluatedaccording to the period during which the transfer is completed, and thetransfer completion time is calculated (step S35 or S36).

[0190] The steps of the process for predicting the execution time of aread command is similar in detail to the aforementioned steps of theprocess for predicting the execution time of a write command, and willnot be described any further.

[0191] As described above, the disk apparatus according to the firstembodiment internally executes the prediction process, and thus canaccurately predict the execution time of an I/O command. Also, executionof an I/O command is determined by comparing the predicted executiontime with the maximum tolerable execution time constituting a deadline.In this way, the disk apparatus executes the process for time managementof I/O commands by itself and thus can accurately define a deadline.

[0192] As a result, the disk apparatus according to the first embodimentcan perform accurate time management taking the execution time intoaccount and can execute the process in real time while avoiding asituation in which a high-priority request most wait for execution.

[0193] <<Embodiment 2>>

[0194] Now, a disk apparatus according to the second embodiment of thepresent invention will be explained. The configuration of a diskapparatus according to the second embodiment is substantially similar tothat of the disk apparatus according to the first embodiment shown inFIG. 1.

[0195] The operation of the HDD control circuit 9 according to thesecond embodiment will be explained with reference to FIG. 8. FIG. 8 isa flowchart showing the operation of the HDD control circuit 9 of thedisk apparatus according to the second embodiment for processing acommand requesting to be transferred.

[0196] As shown in FIG. 8, upon application of a command requesting thetransfer data of an amount of from the external system to the HDDcontrol circuit 9 (step S41), the HDD control circuit 9 predicts thesize of the data that can be input or output within a deadline deliveredas a command parameter, on the basis of: (1) the information about thetarget address; (2) the prevailing operation of the buffer RAM 3 and (3)the head position delivered thereto as command parameters (step S42).Then, the external system is notified of the predicted data size such asa host computer (step S43).

[0197] [Data Size Prediction Process]

[0198] The process of data size prediction in the HDD control circuit 9according to the second embodiment will be described in detail belowwith reference to FIGS. 9 and 10 attached hereto.

[0199]FIG. 9 is a flowchart showing the flow of the process forpredicting the data size that can be written before the deadline.

[0200] As shown in FIG. 9, the HDD control circuit 9 first compares theavailable segment size with the maximum size of the transfer data, i.e.,the amount of data that can be continuously transferred to the bufferRAM 3 before the deadline (step S51).

[0201] In the case where the available segment size is equal to orlarger than the maximum size of the transfer data in step S51, themaximum size of the transfer data is defined as the size of the datathat can be input or output (step S56).

[0202] In the case where the maximum size of the transfer data is largerthan the available segment size in step S51, on the other hand, whetheran overflow will occur during transfer is determined (step S52). In thecase where step S52 determines that no overflow will occur, the maximumsize of the transferred data is determined as the data size that can beinput or output (step S56). Conversely, in the case where it isdetermined that an overflow will occur, the size of the transfer data atthe time that the overflow occurs is calculated (step S53). At the sametime the size of the data transferable during the time length remainingbefore the deadline is calculated (S54). In step S55, the size of thetransfer data at the time of overflow and the size of the transfer dataduring the remaining time are added to each other to calculate the totalsize of the transfer data.

[0203] Now, explanation will be made in detail about each step of thedata size prediction process in the HDD control circuit 9. First, eachparameter for the data size prediction process is defined as follows.

[0204] The transfer rate from the external system to the buffer RAM 3 isdefined as Vb, the write speed into the disk 1 from the buffer RAM 3 asVd (in units of MB/s), the segment size assigned to the write command asMb, the size of the transfer data for the write command as Mc (in unitsof kB), and the deadline as Tmax (in units of ms).

[0205] Also, as a function of time t (in units of ms), the segmentaccumulation amount at time point t is defined as Ms(t) (in units ofkB), and the change in the remaining data transferred to the segment inresponse to the previous command as of time point t as Md(t) (in unitsof kB).

[0206] As in the process according to the first embodiment describedabove, the period before the transfer data are written finally in thedisk is divided into four time zones described below for calculation ofthe segment accumulation amount, etc.

T1 period: 0<t Tw1   (1)

[0207] The T1 period provides the head seek and rotational latency timedue to the command issued before the predicted time point.

T2 period: Tw1<t Tw1+Td1   (2)

[0208] During the T2 period, data is written into the disk in responseto a command issued before the predicted time point.

Td1=Md(0)/Vd

T3 period: Tw1+Td1<t/Tw1+Td1+Tw2   (3)

[0209] The T3 period provides the head seek and rotational latency timedue to a new command issued in the future.

T4 period: Tw1+Td1+Tw2<t Tw1+Td1+Tw2+Td2   (4)

[0210] During the T4 period, data are written into the disk in responseto a new command issued in the future.

[0211] The periods T1 to T3 remain unchanged by the size of the transferdata, but the T4 period is variable with the size of the transfer data.

[0212] Now, explanation will be made in detail about the steps of theprocess for predicting whether the data has a size that can be writtenwithin the deadline providing the maximum tolerable execution time.

[0213] Step S51: Comparison between available segment size and maximumsize of transfer data

[0214] The available segment size (Mb−Ms(0)) as of the predicted timepoint and the maximum size Mmax of the transfer data are compared witheach other. Mmax is the size of the data that can be transferredcontinuously to the buffer RAM before deadline, and is given by equation(17).

Mmax=Vb×Tmax   (17)

[0215] Step S52: Determines the occurrence of overflow.

[0216] Assume that the available segment size is not more than themaximum size of the transfer data.

[0217] In view of the possibility of segment overflow occurring duringthe data transfer, it is necessary to calculate the memory accumulationamount during the data transfer and to determine whether an overflowoccurs or not.

[0218] The condition for occurrence of an overflow is that the segmentaccumulation amount Ms(t) outgrows the segment size Mb before the dataamount Mmax is continuously transferred to the buffer RAM 3, andtherefore is expressed by equation (18).

Md(Tovf)+Vb×Tovf=Mb and Tovf Mmax/Vb   (18)

[0219] Substituting equations (3) and (4) into equation (18) gives theoverflow time Tovf, thus making it possible to determine whether anoverflow occurs or not.

[0220] Step S53: Calculation of the transfer data size as to whether anoverflow occurs.

[0221] The size Movf of the transfer data at the time of overflowoccurrence is given by equation (19).

Movf=Vb×Tovf   (19)

[0222] Step S54: Calculation of the data size transferred during theremaining time

[0223] During the remaining time from an overflow to the deadline, asmuch data as was written from the buffer RAM 3 to the disk 1 can betransferred from the external system to the buffer RAM 3.

[0224] The situation is classified according to which of the T1 to T4periods includes the deadline and the overflow time point. The time iscalculated during which data can be written into the disk 1 from thebuffer RAM 3 between the overflow and the deadline. The data size Mdtransferable during the remaining time is calculated on the basis of thecalculated writable time and the write speed Vd.

[0225] (1) In the case where the deadline is included in T1 period:

[0226] No data is written from the buffer RAM 3 to the disk 1 during theremaining time between the overflow and the deadline. Therefore, thebuffer RAM 3 continues to overflow and therefore data cannot betransferred thereto. The size Md(in units of kB) of the data transferredduring the remaining time is zero.

Md=0   (20)

[0227] (2) In the case where the deadline is included in T2 period:

[0228] Depending on whether an overflow occurs during T1 or T2 period,the size Md (in units of kB) of the data transferred during theremaining time is given by the following two equations.

[0229] In the case where an overflow occurs during T1 period:

Md=Vd×(Tmax−Tw1)   (21)

[0230] In the case where an overflow occurs during T2 period:

Md=Vd×(Tmax−Tovf)   (22)

[0231] (3) In the case where the deadline is included in T3 period:

[0232] Depending on whether an overflow occurs during in the time periodT1 to T3, the size Md of the data transferred during the remaining timeis given one of the following three equations (23), (24) and (25).

[0233] In the case where an overflow occurs during T1 period:

Md=Vd×Td1   (23)

[0234] In the case where an overflow occurs during T2 period:

Md=Vd×(Tw1+Td1−Tovf)   (24)

[0235] In the case where an overflow occurs during T3 period:

Md=0   (25)

[0236] (4) In the case where the deadline is included in T4 period:

[0237] Depending on whether an overflow occurs during the period T1 toT4 , the size Md of the data transferred during the remaining time isgiven one of the following four equations (26), (27), (28) and (29).

[0238] In the case where an overflow occurs during T1 period:

Md=Vd×(Td1+Tmax−Tw1−Td1−Tw2)   (26)

[0239] In the case where an overflow occurs during T2 period:

Md=Vd×(Tmax−Tovf−Tw2)   (27)

[0240] In the case where an overflow occurs during T3 period:

Md=Vd×(Tmax−Tw1−Td1−Tw2)   (28)

[0241] In the case where an overflow occurs during T4 period:

Md=Vd×(Tmax−Tovf)   (29)

[0242] Step 55: Calculation of the total size of the transfer data.

[0243] The total size Ma (in units of kB) of the transfer data iscalculated as the sum of Movf determined from the above-mentionedequation (19) and Md determined from equations (20) to (29)

Ma=Movf+Md   (30)

[0244] Step 56: Calculation of the total size of the continuouslytransferred data.

[0245] In the case where Mb−Ms(0) b Mc, all the data can be continuouslytransferred from the external system to the buffer RAM 3, and thereforethe total size Ma of all the transferred data is calculated from thefollowing equation.

Ma=Vb×Tmax   (31)

[0246]FIG. 10 is a flowchart showing the flow of the process forpredicting the data size readable before the deadline.

[0247] As shown in FIG. 10, the HDD control circuit 9 first compares thepreread data size in the segment with the maximum transfer data size,i.e., the size of the data transferred and continuously read from thebuffer RAM 3 before the deadline (step S61).

[0248] In the case where the size of the preread data is larger than themaximum transfer data size in step S61, the maximum transferred datasize is defined as the data size that can be input or output (step S66).

[0249] In the case where the maximum transfer data size is larger thanor equal to the size of the preread data, on the other hand, thepossibility of an underflow occurring during transfer is determined(step S62). In the case where the determination in step S62 is that nounderflow occurs, the maximum transfer data size is defined as the datasize that can be input or output (step S66). Conversely, in the casewhere the determination is that an underflow occurs, the calculation ofthe transfer data size as of the time of an underflow (step S63) and thecalculation of the data size that can be transferred during theremaining time before the deadline (step S64) are carried out. Thetransfer data size as of the time point of underflow and the transferreddata size during the remaining time are added to each other thereby tocalculate the total size of the transfer data (step S65).

[0250] The process of predicting the readable data size is similar indetail to that of the writable data size described above, and will notbe explained any further.

[0251] As described above, the disk apparatus according to the secondembodiment can accurately predict the data size that can be input oroutput within the deadline by predicting the data size that can be inputor output within the deadline in the disk apparatus.

[0252] Consequently, the disk apparatus according to the secondembodiment can carry out time management taking the execution time intoaccount and thus can process data in real time while preventing ahigh-priority request from waiting for execution. Further, this diskapparatus can transfer the maximum data size that can be transferredwhile guaranteeing meeting the deadline. Therefore, in addition toguaranteeing the execution time of a high-priority request, a maximumtransfer rate is granted for a low-priority request, resulting in animproved processing efficiency.

[0253] The segments, which are assigned to write and read commandsseparately according to the first and second embodiments describedabove, can alternatively be assigned in accordance with the order ofpriority.

[0254] Also, unlike in the first and the second embodiments explainedwith reference to the case where only one previously-issued commandexists in the segments as of the time of prediction processing, theexecution time and the transferable data size can be calculated in asimilar manner in the case where there exist data due to two or morecommands.

[0255] Further, apart from the first and the second embodiments in whichthe deadline is sent to the HDD as a command parameter each time ofprediction processing, the deadline can alternatively be set in advanceby another command.

[0256] <<Embodiment 3>>

[0257] Now, explanation will be made about a disk apparatus according toa third embodiment of the present invention. The configuration of thedisk apparatus according to the third embodiment is substantiallysimilar to that of the disk apparatus according to the first and secondembodiments shown in FIG. 1.

[0258] The operation of the HDD control circuit 9 according to the thirdembodiment will be explained with reference to FIG. 11 attached hereto.

[0259]FIG. 11 is a flowchart showing the operation for processing acommand requesting a transfer data amount by the HDD control circuit 9according to the third embodiment.

[0260] As shown in FIG. 11, upon application of a command requesting atransfer data amount from an external system to the HDD control circuit9 (step S71), the HDD control circuit 9 determines whether the inputcommand represents a request for the read data size, a request for thepreread data size or a request for the write data size (steps S72, S73,and S74). The preread data size is defined as the data size stored inthe temporary memory circuit from the disk.

[0261] In the case where the input command represents a request for theread data size, the preread data size of a corresponding segment is setas the transfer data size (step S75). In the case where the inputcommand represents a request for the preread data size, on the otherhand, the size of the corresponding available segment is set as the sizeof the preread data (step S76). Also, in the case where the inputcommand represents a request for the write data size, the size of thecorresponding vacant segment is set as the transferred data size (stepS77).

[0262] Finally, the external system is notified of each data size thusset (step S78).

[0263] As described above, in the disk apparatus according to the thirdembodiment, the buffer RAM 3 of the disk apparatus is checked for thetransferable data size, and the external system is notified of the sizeof an available size of a corresponding segment or the size of thepreread data. As a result, data can be transferred continuously betweenthe external system and the disk apparatus in bursts, and the executiontime of an I/O request can be calculated from the size of the data to betransferred and the bus transfer rate alone. In this way, in the diskapparatus according to the third embodiment, the execution time of anI/O request can be accurately and easily calculated, therebyfacilitating the time management. Also, the disk apparatus according tothe third embodiment can produce the effect of reducing the occupiedtime of the I/O bus since the data I/O can always be accomplished bytransfer in bursts.

[0264] <<Embodiment 4>>

[0265] Now, an explanation will given of a disk apparatus and an I/Ocontrol method according to a fourth embodiment of the presentinvention. The configuration of the disk apparatus according to thefourth embodiment is substantially similar to that of the disk apparatusaccording to the first embodiment shown in FIG. 1. The disk apparatus 31according to the fourth embodiment is different from that of otherembodiments in the control method of the HDD control circuit 9.Specifically, commands are processed differently with added processingsteps.

[0266]FIG. 12 is a block diagram showing a configuration of a videoprocessing apparatus as an external system for recording and reproducingthe video signal using the I/O control method according to the fourthembodiment.

[0267] In FIG. 12, a video processing apparatus 32 is connected to thedisk apparatus 31 through an interface bus 33. The video processingapparatus 32 includes a microprocessor 34, a buffer memory 35 which is atemporary memory circuit, an interface circuit 36 for controlling theinput and output to and from the interface bus 33 and a video dataprocessing circuit 37 for compressing or expanding the video data.

[0268]FIG. 13 is a diagram showing a method of segmenting the buffer RAM3 of the disk apparatus 31 according to the fourth embodiment. Thebuffer RAM 3 is segmented into a write buffer area 3 a and a read bufferarea 3 b.

[0269] The video processing apparatus 32 configured as described aboveissues various requests, i.e., various commands to the disk apparatus31. Commands requiring data transfer include a write command making up arequest for writing data, a preread command making up a request forprereading a single data block, a read command making up a request forreading data, and an auto read command for requesting an automaticreading operation by the disk apparatus 31.

[0270] Also, the disk apparatus 31 corresponds to the transfer sizerequest command. Upon issue of a command requesting a transfer size fromthe video processing-apparatus 32, therefore, the disk apparatus 31notifies the video processing apparatus of a data size that can becontinuously transferred.

[0271] In the case of issuing a write command or a read command, thecommand type, the transfer data amount, the data recording position,etc. are sent to the disk apparatus 31 as data parameters. The datarecording position is designated using a logical address logicallyassigned to the disk 1.

[0272] The command requesting the transfer data size is issued to thedisk apparatus 31 together with the type of the transfer data sizerequested. The disk apparatus 31 notifies the video processing apparatusof the data size that can be transferred continuously based on theaccumulated condition of the buffer RAM 3. The operation for processingthe command requesting the transfer size in the disk apparatus 31 issimilar to the process described above with reference to FIG. 11 showingthe third embodiment.

[0273] The auto read command, on the other hand, is issued periodically,prior to reading the video data. The file management information tableused for the auto read command is generated by the video processingapparatus 32, transferred to the disk apparatus 31 and recorded in thedisk 1.

[0274] The recording format of the file management information tableaccording to the fourth embodiment is shown in FIG. 19. FIG. 19 is adiagram for explaining the file management information according to thefourth embodiment. Columns A1, A2 and A3 represent regions for storingsuch parameters as the frame number, the logic address and the dataamount of the frame data making up the video file recorded in the disk1. These parameters are recorded for all the frames making up the videofile. The operation of the video processing apparatus 32 and the diskapparatus 31 according to the fourth embodiment having theabove-mentioned configuration will be explained below with reference toeach command.

[0275] [Write Command]

[0276] First, explanation will be made about the procedure in which thevideo processing apparatus 32 issues a write command.

[0277] In response to a periodic request of the microprocessor 34, avideo data processing circuit 37 generates a data block by compressingthe video data for each display unit, and stores it temporarily in abuffer memory 35.

[0278] Then, an I/O control method executed by the microprocessor 34will be explained with reference to FIG. 14. FIG. 14 is a flowchartshowing the I/O control operation performed in the microprocessor 34.

[0279] First, step S81 issues a command requesting a transfer data sizeto the disk apparatus 31 and receives the amount of the continuouslywritable data.

[0280] Step S82 compares the continuously writable data amount with theamount of data to be transferred, and determines whether or not theblock transfer (continuous transfer of each data block) is possible. Ifthe block transfer is possible, the process proceeds to step S83, whileif the block transfer is impossible, the process proceeds to step S85for a determination.

[0281] Step S83 issues a write command corresponding to the data block,and executes the block transfer in a predetermined procedure. In thecase where a plurality of data blocks are stored in the buffer memory35, the above-mentioned block transfer process is repeated a pluralityof times.

[0282] Step S84 determines whether data remains in the buffer memory 35.In the case where data remains, the process proceeds to step S85, whileif no data remains, the process is terminated.

[0283] In step S85, the amount of continuously writable data is comparedwith a preset minimum data amount for starting the write operationthereby to determine whether the amount of the continuously writabledata is not less than the minimum data amount for starting the writeoperation. In the case where the amount of continuously writable data isnot less than the minimum data amount for starting the write operation,the data block is segmented in step S86. In step S86, a write commandfor the data thus segmented is issued, and the data transfer isexecuted.

[0284] In the case where the above-mentioned condition is not fulfilled,in contrast, the process is terminated as it is. The minimum data amountfor starting the write operation can be appropriately set to apredetermined value such as one half of the size of the data block inadvance.

[0285] Now, the operation of processing the write command from the videoprocessing apparatus 32 in the disk apparatus 31 will be explained withreference to FIG. 1.

[0286] The data corresponding to the write command is stored in thebuffer data RAM 3 by the interface circuit 2. The HDD control circuit 9determines a corresponding available segment size from the data amountstored in the buffer RAM 3 and changes the amount of continuouslywritable data. The data temporarily stored in the buffer RAM 3 issequentially recorded in the disk 1.

[0287] [Preread Command with Command ID]

[0288] Now, explanation will be made about the procedure in which thevideo processing apparatus 32 shown in FIG. 12 issues a preread command.

[0289] In response to a periodic request from the microprocessor 34, theinterface circuit 36 issues a preread command with a command ID. Thecommand ID is an identifier of a preread command and is set as adifferent value for each command.

[0290] Now, the operation of processing the preread command with commandID in the disk apparatus 31 will be explained with reference to FIGS. 1and 15. FIG. 15 is a flowchart showing the operation of processing thepreread command with a command ID.

[0291] In step S91 shown in FIG. 15, a series of processes describedbelow are executed.

[0292] First, the HDD control circuit 9 shown in FIG. 1 reproduces thedata based on the logic address notified from the video processingapparatus 32, and stores in the buffer RAM 3 as preread data. Further,the HDD control circuit 9 changes the amount of continuously readabledata in accordance with the amount of the preread data stored in thebuffer RAM 3.

[0293] In step S92, the management information for the preread data isstored in a preread data management table as shown in FIG. 16. FIG. 16is a diagram an example of the preread data management table. In FIG.16, columns B1, B2 and B3 represent regions for storing such parametersas a command ID (identifiers), a storage position (start address) in thebuffer RAM 3 and a data amount, respectively. These regions store eachdata preread in response to a preread command with a preread ID.

[0294] [Read Command with Command ID]

[0295] Now, the procedure in which a read command with a command ID isissued by the video processing apparatus 32 will be explained withreference to FIG. 17. FIG. 17 is a flowchart showing the process ofissuing a read command with a command ID. The read command is issuedafter the preread command for the same data. Also, the read command isassigned the same command ID as the preread command and issued to thedisk apparatus 31.

[0296] In step S101, a command requesting the transfer data size isissued to the disk apparatus 31, and receives the amount of continuouslyreadable data, i.e., a preread data amount.

[0297] Step S102 determines whether data can be read by block based onthe amount of continuously readable data. In the case where the data canbe read by block, step S103 is executed, otherwise the process proceedsto step S105.

[0298] In step S103, a read command with a command ID with command IDcorresponding to a data block is issued and data blocks are read outcontinuously in a predetermined procedure. In the case where a pluralityof data blocks are stored in the buffer RAM 3, the above-mentioned blocktransfer process is repeated a plurality of times.

[0299] Step S104 determines whether data remains in the buffer RAM 3. Inthe case where data remains so, the process proceeds to step S105.Otherwise, the process is terminated.

[0300] In step S105, the amount of continuously readable data iscompared with a preset minimum data amount for starting the readoperation thereby to determine whether the amount of continuouslyreadable data is not less than the minimum data amount for starting theread operation. In the case where the condition is fulfilled that theamount of continuously readable data is not less than the minimum dataamount for starting the read operation, step S106 is executed. In thecase where the above-mentioned condition fails to be fulfilled, theprocess is terminated immediately. The minimum data amount for startingthe write operation is set appropriately to a predetermined value suchas one half the data amount of a data block.

[0301] In step S106, the data block is segmented, and a read commandwith command ID corresponding to the segmented data is issued. In stepS106, the segmented data are continuously read out.

[0302] Now, in the disk apparatus, the operation of processing the readcommand with command ID described above issued from the video processingapparatus 32 will be explained with reference to FIG. 18. FIG. 18 is aflowchart showing the operation of processing a read command a in thedisk apparatus 31 with command ID.

[0303] In step S111, data corresponding to the command ID of the readcommand is retrieved and selected from the preread data managementtable.

[0304] In step S112, the selected data is output to the video processingapparatus 32. In step S113, the disk apparatus deletes the items of datawhich have been completely transferred from the preread data managementtable shown in FIG. 16.

[0305] [Auto Read Command]

[0306] Now, explanation will be made about the process for issuing anauto read command by the video processing apparatus 32.

[0307] The video processing apparatus 32 determines the prereadparameters including the identifier of the file management informationtable for the file to be preread, the frame number (F0) to be prereadfirst, the number of frames to be preread (NF), the number of skips (S)indicating the intervals of the frame numbers to be preread and thepreread direction (D), and issues an auto read command to the diskapparatus 31 as a command parameter.

[0308] In what is called the “fast forward playback” for displayingvideo data at predetermined frame intervals, the preread operation isexecuted by setting the number S of skips to a predetermined value. Thedata preread is read and displayed at time intervals similar to the caseof recording the data. The preread direction D is set to “0” whenprereading in the order of recording, while it is set to “1” forprereading in reverse order.

[0309] In response to the auto read command, the disk apparatus 31issues sequential read commands with a data recorded position as aparameter corresponding to each frame. The data preread by the bufferRAM 3 is output from the disk apparatus 31 to the video processingapparatus 32.

[0310] Now, in the disk apparatus, the operation of processing the autoread command supplied from the video processing apparatus 32 will beexplained with reference to FIG. 20. FIG. 20 is a flowchart showing theoperation of processing the auto read command in the disk apparatus 31.

[0311] First, step S121 reproduces the file management information fromthe file management information table on the disk 1. In step S122, aframe to be preread is selected based on the file management informationreproduced, thereby reading the data amount and the start addresscorresponding to the selected frame. The frame number (FP) to be prereadis determined by the following equation;

FP=F0+(−1)D×S×(N−1),

[0312] where N is the number of processing times in step S122. D is thepreread direction which is “0” when prereading in the order of recordingand “1” when reading in the reverse order.

[0313] In step S123, the data block corresponding to the selected frameis reproduced and stored in the buffer RAM 3.

[0314] Next, step S124 compares the number N of processing times withthe number NF of the frames to be preread and determines whether thepreread operation is complete. In the case where the preread operationis incomplete, the above-mentioned process is continued. In the casewhere the preread operation is complete, in contrast, theabove-mentioned process is completed.

[0315] If the data are preread by the buffer RAM 3, like in the prereadcommand described above, the HDD control circuit 9 changes the amount ofcontinuously readable data in accordance with the amount of prereaddata. The HDD control circuit 9 then informs the external system inresponse to the transfer data size request from the video processingapparatus 32.

[0316] As described above, according to the I/O control method of thefourth embodiment, the video processing apparatus 32 receives the amountof continuously transferable data from the disk apparatus and controlsthe transfer based on the received amount of continuously transferabledata. As a result, the I/O control method according to the fourthembodiment permits data to be continuously transferred always betweenthe video processing apparatus 32 and the disk apparatus 31. In thisway, the predicted execution time can be accurately predicted andmanaged, while at the same time reducing the processing load of thevideo processing apparatus.

[0317] Further, in the disk apparatus according to the fourthembodiment, the auto preread operation is executed based on the filemanagement information of the image file stored in the disk apparatus31. As a result, the preread operation suitable for the image canexecuted with the disk apparatus alone, thereby realizing a reduced loadon the video processing apparatus and the efficient operation of thebuffer memory.

[0318] Furthermore, in the disk apparatus according to the fourthembodiment, the preread data can be directly designated and accessedusing the command ID. Therefore, the process of retrieving the prereaddata can be eliminated in the disk apparatus, resulting in a reducedprocessing load of the disk apparatus for the preread processing on theone hand and an efficient use of the buffer memory on the other hand.

[0319] Although the fourth embodiment concerns the case in which thefile management table for video data is prepared by the video processingapparatus and notified to the disk apparatus, the file managementinformation can alternatively be produced in the disk apparatus bydesignating a file identifier in the process of writing the video data.

[0320] According to the fourth embodiment, the data blocks selected aresequentially preread in response to an auto read command, and are outputsequentially to the video processing apparatus in response to a readcommand. As an alternative, the selected data blocks can be outputdirectly to the video processing apparatus in response to an auto readcommand.

[0321] <<Embodiment 5>>

[0322] Now, a disk apparatus according to a fifth embodiment of thepresent invention will be explained. The video processing apparatusaccording to the fifth embodiment has a substantially similarconfiguration to the video processing apparatus shown in FIG. 12, andthe disk apparatus has a substantially similar configuration to the diskapparatus shown in FIG. 1. The fifth embodiment is different from otherembodiments in that the video processing apparatus 32 issues six typesof I/O commands in accordance with the type of data and in that the diskapparatus performs the processing operation in accordance with the typeof each I/O command.

[0323] The video processing apparatus 32 according to the fifthembodiment issues, for a sequential data, a sequential write commandmaking up a write request, a sequential preread command making up apreread request, and a sequential read command making up a read request.Further, the video processing apparatus 32 according to the fifthembodiment issues for random data, a random write command making up awrite request, a random preread command making up a preread request anda random read command making up a read request.

[0324] The operation of the disk apparatus 31 corresponding to each ofthe above-mentioned commands will be explained with reference to FIG.21. FIG. 21 is a flowchart for each command issued to the disk apparatus31.

[0325] First, explanation will be made about the operation correspondingto the sequential write command or the random write command.

[0326] In step S131, the type of the command is determined. In the caseof a random write command, step S132 performs the recording operation ina procedure similar to the first embodiment described above, while inthe case of a sequential write command, the process proceeds to stepS133.

[0327] Step S133 determines whether the data amount stored in the bufferRAM 3 is larger than the maximum amount of data that can be accumulated.In the case where the determination is affirmative, step S134 isexecuted. Otherwise, the process is immediately terminated. The maximumdata amount capable of being accumulated can be set based on the dataamount storable in the buffer RAM 3, etc. in accordance with thesequential write command to be issued next.

[0328] In step S134, the data stored in the buffer RAM 3 arecontinuously recorded in the disk 1. In view of the fact that thesequential data stored in the buffer RAM 3 are recorded in substantiallysuccessive regions on the disk 1, a large amount of data can be recordedwithin a short time without any overhead time, such as required for theseek operation and the rotational latency time.

[0329] Now, the operation corresponding to a sequential preread commandor a random preread command will be explained with reference to FIG. 22.FIG. 22 is a flowchart showing the operation associated with thesequential preread command or the random preread command.

[0330] First, step S141 identifies the command type. In the case of arandom preread command, step S142 performs a preread operation in aprocedure similar to the first embodiment described above. In the caseof a sequential preread command, on the other hand, the process proceedsto step S143.

[0331] In step S143, the sequential preread commands are accumulated.

[0332] Step S144 determines whether the sequential preread commands thusaccumulated are greater than or equal to the maximum number of commandsthat can be accumulated. In the case where the condition is fulfilledthat the accumulated sequential preread commands are greater than orequal to the maximum number of commands that can be accumulated, thenstep S142 continuously reproduces the data corresponding to a pluralityof the accumulated commands. In the case where the above-mentionedcondition fails to be met, on the other hand, the process is terminated.

[0333] The disk apparatus 31 according to the fifth embodiment alsoperforms the prefetch operation as an internal process.

[0334] The prefetch operation is for reproducing and storing in thebuffer RAM 3 the data around the recording positions of the datacorresponding to the commands. According to the fifth embodiment, aparameter indicating the advisability of the prefetch operation istransmitted to the disk apparatus 31 at the time of issuing eachcommand.

[0335] The selection procedure in the prefetch operation by the diskapparatus 31 will be explained with reference to FIG. 23. FIG. 23 is aflowchart showing the prefetch operation in the disk apparatus 31.

[0336] First, step S151 executes the operation of prereading the datacorresponding to the random preread command or the sequential prereadcommand in a procedure similar to that of the first embodiment describedabove

[0337] Step S152 determines the advisability of the prefetch operationbased on the parameters notified from the video processing apparatus 32.In the case where the prefetch operation is permitted in step S152, theprefetch operation is executed in step S153. In the case where theprefetch operation is not permitted, in contrast, the process isterminated immediately. Especially in the case of game play of videodata by the video processing apparatus 32, a plurality of data stored atdistant recording points on the disk 1 are often reproducedsequentially. In such a case, the prefetch operation often degrades theresponse to each command.

[0338] In the case where a random preread command is issued after theprefetch operation, on the other hand, the first process executed is tocheck whether or not the corresponding prefetched data is the buffer RAM3 or not. If the data has been prefetched, the possibility of readingthe data is transmitted to the video processing apparatus 32.

[0339] As described above, the disk apparatus according to the fifthembodiment can switch the size of data recorded continuously in the diskor the number of commands continuously read, in accordance with thecommand type. For this reason, the disk apparatus according to the fifthembodiment can improve the processing performance of the image datawhile at the same time making it possible to use the buffer memoryefficiently.

[0340] Also, the disk apparatus according to the fifth embodiment canselect the prefetch operation according to the command type, andtherefore can use the buffer memory efficiently. Further, the diskapparatus according to the fifth embodiment can improve the response toa random data I/O request, can prevent the delayed response due to theunrequired prefetch operation in response to a sequential data I/Orequest, and thus can improve the processing efficiency of the diskapparatus as a whole.

[0341] <<Embodiment 6>>

[0342] Explanation will be made below about a disk apparatus accordingto a sixth embodiment of the present invention. The video processingapparatus according to the sixth embodiment has a configurationsubstantially similar to that of the video processing apparatus shown inFIG. 12, and the disk apparatus is also substantially similar inconfiguration to the disk apparatus shown in FIG. 1. The sixthembodiment is different from other embodiments in that the videoprocessing apparatus issues a sequential write command with a time limitand a sequential preread command with a time limit (both commands arehereinafter referred to collectively as the sequential data I/O request)and in that the disk apparatus performs the processing corresponding toeach of these commands.

[0343] The random write command and the random preread command(hereinafter referred to collectively as the random data I/O request),on the other hand, are normal I/O commands free of a time limit.

[0344] The operation of the disk apparatus 31 in response to theabove-mentioned commands sill be explained with reference to FIG. 24.FIG. 24 is a flowchart showing the operation of processing the commandssupplied from the video processing apparatus 32 in the disk apparatus31.

[0345] First, step S161 identifies the command type. In the case wherethe command represents a sequential data I/O request in step S161, theprocess proceeds to step S162, while in the case where the command is arandom data I/O request, on the other hand, the process proceeds to stepS164.

[0346] In step S162, the time limit transmitted from the videoprocessing apparatus 32 is extended in accordance with the availablecapacity of the buffer RAM 3. The extension time can be appropriatelyselected in accordance with the data amount of the data blockcorresponding to the sequential data I/O request or in accordance withthe sequential data I/O request.

[0347] In step S163, the command is accumulated on a requestaccumulation queue shown in FIG. 25. FIG. 25 is a diagram for explainingthe sequential request accumulation queue (a) and a random requestaccumulation queue (b). Columns C1 and D1 represent storage areas at therecording positions (LBA) on the disk 1, and the columns C2 and D2represent the storage areas of the data amount. The column C3 storestime margins based on the time limit calculated in step S162. This timemargin is calculated as a remaining time usable for the processing. Inthe sequential data I/O request accumulation queue, commands arearranged in an ascending order of time margin from the first row (No.1). In the random data I/O request accumulation queue, on the otherhand, commands are arranged in the order of issue.

[0348] In step S164, it is determined whether requests have beenaccumulated in the sequential data I/O requests accumulation queue. Inthe case where requests have been accumulated, the process proceeds tostep S165. In the case where requests are not accumulated, step S167executes the request on the first row of the random data I/O requestaccumulation queue.

[0349] In step S165, the first request in the sequential data I/Orequest accumulation queue is selected and it is determined whether thetime margin is larger than a command select reference time. In the casewhere the time margin is greater than or equal to a predetermined value,the process proceeds to step S168, while in the case where the timemargin is smaller than a predetermined value, step S166 executes therequest on the first row of the sequential data I/O request accumulationqueue. The command select reference time can be set appropriately on thebasis of the time predicted in advance as a time required for processinga sequential data I/O request.

[0350] In step S168, it is determined whether commands have beenaccumulated in the random data I/O request accumulation queue. In thecase where commands are not so accumulated, the process proceeds to stepS170. In the case where commands have been accumulated, step S169executes the processing corresponding to the first-row command of therandom data I/O request accumulation queue.

[0351] In step S170, the command on the first row of the sequential dataI/O request accumulation queue is selected as a command to be executed.While the head is moving from the present position to a physicalposition corresponding to the command to be executed, a command that canbe recorded and reproduced is retrieved, and the retrieved command isinterpreted as a command to be selected. In step S171, the scheduledexecution time is compared with the time margin of the command to beexecuted on the assumption that a command to be selected is processedbefore a commands to be executed, and determination is made as towhether the command to be executed can be completely processed withinthe time margin. In the case where the command to be executed can beprocessed, step S172 inserts the command to be selected on the first rowof the sequential data I/O request accumulation queue, followed byexecution of step S173. In the case where the command to be executed isimpossible to process in step S171, the process immediately proceeds tostep S173.

[0352] Step S173 executes the process in response to the requestaccumulated on the first row of the accumulation queue.

[0353] As described above, in the disk apparatus according to the sixthembodiment, the order of storage process is selected in accordance withthe time limit and the available capacity of the buffer RAM 3. As aresult, the disk apparatus according to the sixth embodiment canincrease the speed of a response to a random data I/O request while atthe same time guaranteeing a real-time response to a high-prioritysequential data I/O request, thereby improving the processing efficiencyof the disk apparatus. Thus, it is possible to solve the problem of aconsiderably delayed response to random data I/O requests.

[0354] Also, in the disk apparatus according to the sixth embodiment,the order of processing a request is selected in accordance with thetime limit and the physical address on the disk. Therefore, thereal-time response to a request is guaranteed and the time required forhead seek operation is reduced. Thus the processing efficiency of thedisk apparatus is improved. Further, according to the sixth embodiment,the order of processing accumulated requests is determined based on thephysical address, and therefore it is possible to predict and manage theexecution time of each request accurately.

[0355] <<Embodiment 7>>

[0356] Now, a disk apparatus according to a seventh embodiment of thepresent invention will be described.

[0357]FIG. 26 is a block diagram showing a configuration of a diskapparatus according to the seventh embodiment.

[0358] As shown in FIG. 26, the disk apparatus according to the seventhembodiment is connected to an external system (not shown) such as a hostcomputer through a host I/O bus 101. The disk apparatus according to theseventh embodiment comprises a CPU 42 for controlling each circuit, abuffer RAM 43 constituting a memory circuit for storing datatemporarily, a read/write signal processing circuit 44 for encoding anddecoding the data, a head-disk assembly 45, an actuator drive circuit 48and a HDD control circuit 49.

[0359] The head-disk assembly 45 includes a disk 41, a head assembly 46and an actuator 47. The actuator 47 is driven by the actuator drivecircuit 48. The CPU 42 controls the buffer RAM 43, the read/write signalprocessing circuit 44 and the actuator drive circuit 48 through the HDDcontrol circuit 49.

[0360]FIG. 27 is a block diagram showing a configuration of the HDDcontrol circuit 49.

[0361] As shown in FIG. 27, the HDD control circuit 49 includes a hostinterface circuit 51 constituting an interface circuit with the externalsystem, a CPU interface circuit 52 making up an interface circuit withthe CPU 42, a buffer control circuit 53 for controlling the buffer RAM43, and a control signal I/O circuit 54 for applying or supplied with acontrol signal to or from the read/write signal processing circuit 44and the actuator drive signal 48 of the disk apparatus.

[0362]FIG. 28 is a diagram showing the correspondence between thesegment setting register 61 in the buffer control circuit 53 and eachsegment of the buffer RAM 43 of the disk apparatus.

[0363] As shown in FIG. 28, the buffer RAM 43 is divided into N segments#1 to #N. Each segment of the buffer RAM 43 corresponds to the registersREG#1 to REG#N of the segment setting register 61. Each of the registersREG#1 to REG#N has set therein values including an access type CSN, asegment start address ASN, a segment size MSN, a disk transfer priorityorder PDN, a disk transfer block size MBD and a host transfer block sizeMBN. The number N of segments is the total number of the segments and isinvariable.

[0364] The access type CSN is the number for setting the access type tothe associated segment from the external system and is divided intothree different types including: (1) write-only, (2) read-only and (3)read-write. The segment start address ASN is the start address of agiven segment in the buffer RAM 43, and the segment size MSN is the sizeof a given segment. Both ASN and MSN are expressed in terms of sectors.One sector represents 512 bytes.

[0365] The disk transfer priority order PDN, the disk transfer blocksize MBDN and the host transfer block size MBHN are values for settingthe conditions for starting/stopping the host transfer between theexternal system and each segment and the disk transfer between thesegments and the disk, respectively.

[0366] The disk transfer priority order PDN indicates the order ofpriority in which data are transferred between each segment and thedisk. PDN is set in values of 1 to N. The disk transfer block size MBDNgives a unit of data transfer, by sector, between each segment and thedisk. The host transfer block size MBHN represents a unit of datatransfer, in terms of sectors, between each segment and the host.

[0367] Now, the operation of each part of the disk apparatus will beexplained with reference to FIGS. 26, 27 and 28.

[0368] The host interface circuit 51 of the HDD control circuit 49 issupplied with data, commands and parameters from an external systemthrough the host I/O bus 101. In the host interface circuit 51, data areoutput to the buffer control circuit 53 through an internal bus 201, andcommands and parameters are applied to the internal bus 202. The hostinterface circuit 51 is supplied with the data read from the buffer RAM43 through the buffer control circuit 53 and the internal bus 201. Acommand response from the CPU 42 is applied to the host interfacecircuit 51 through the CPU interface circuit 52 and the internal bus202. The read data and the responses to commands are output to theexternal system through the host I/O bus 101.

[0369] The buffer control circuit 53 is connected to the buffer RAM 43through the RAM I/O bus 103, and controls the data input and output toand from the buffer RAM 43 in accordance to each value set in thesegment setting register 61. The data input to and output from thebuffer RAM 43 include those input to and output from the external systemthrough the host interface circuit 51, those input to and output fromthe CPU 42 through the CPU interface circuit 52, and those input to andoutput from the read/write signal processing circuit 44 through theread/write I/O bus 104. The segment setting register 61 of the buffercontrol circuit 53 is set by the CPU 42.

[0370] The read/write signal processing circuit 44 (FIG. 26) receivesand encodes the write data from the buffer RAM 43 through the buffercontrol circuit 53 of the HDD control circuit 49. The write data thusencoded is output to a head 46 a as a write signal through a signal line107. Also, the read/write signal processing circuit 44 receives anddecodes the read signal read out by the head 46 a from the disk 41through the signal line 107. The read signal thus decoded is applied tothe buffer RAM 43 as a read data through the buffer control circuit 53.

[0371] The actuator drive circuit 48 outputs a drive signal 108 to theactuator 47 on the basis of an actuator control signal 106 from thecontrol signal I/O circuit 54 of the HDD control circuit 49. This drivesignal drives the actuator 47 so that the head 46 a is moved through thehead assembly 46.

[0372] The CPU 42 receives commands and parameters from the externalsystem through the host interface circuit 51 of the HDD control circuit49 and the CPU interface circuit 52. The CPU 42 interprets the commands,controls the buffer control circuit 53, the read/write signal processingcircuit 44 and the actuator drive circuit 48, and thus executes the dataread/write operation. Also, the CPU 42 provides a response to a command,if required, to the external system through the CPU interface circuit 52and the host interface circuit 51.

[0373] The command processing in the disk apparatus configured asdescribed above will be explained below with reference to the drawings.

[0374] [Segment Setting Command]

[0375] Parameters for the segment setting command include the segmentnumber, the access type, the segment size, the disk transfer priorityorder, the disk transfer block size and the host transfer block size.The segment number is an identification number of each segment and isgiven as K where K=1 to N. The access type, the segment size, the disktransfer priority order, the disk transfer block size and the hosttransfer block size, respectively, correspond to each set value of thesegment setting register.

[0376]FIG. 29 is a flowchart showing the processing of the segmentsetting command by the disk apparatus according to the seventhembodiment.

[0377] As shown in FIG. 29, upon application of a segment settingcommand from the external system thereto, the CPU 42 (FIG. 26) acquireseach set value from the parameters of the applied segment settingcommand (step S181), and checks whether the acquired set value isincluded in a predetermined range (step S182). In the case where the setvalue is out of the predetermined range, an error is notified to theexternal system (step S185).

[0378] In the case where a set value is within the predetermined range,the CPU 42 considers the segment #K as an available area(step S183), andcompares the secure segment size with the summed size of available areasnot assigned as a segment (step S184). In the case where the segment islarger than the available area in size, an error message is transmittedto the external system (step S185). In the case where the segment issmaller than the available area in size, on the other hand, the segmentstart address of REG#(K+1) to REG#N is recalculated and set in eachregister (step S186), and each value is set in REG#K (step S187).

[0379]FIG. 30 diagrams an example of changing the segment settingaccording to a segment setting command. The example shown in FIG. 30concerns the case in which the size of the buffer RAM 43 is set to 128kB (kB: 1024 bytes), the total number N of segments is set to 4 and thesize of the segment #3 is changed from 16 kB to 32 kB. FIG. 30 shows thestate before command execution, and FIG. 30 shows the state aftercommand execution.

[0380] When the segment #3 is considered as an available area, the totalsize of the available areas is 48 kB. Since the total size of theavailable areas is not less than 32 kB that is the segment size to beset, the segment start address of the segment #4 is recalculated, andthe start address 4000H is changed to 5000H thus ending the setting.

[0381] [Segment State Request Command]

[0382] Upon application of a segment state request command to the CPU 42from the external system, the CPU 42 checks the segment settingregisters REG#1 to REG#N sequentially, and outputs the set value of eachregister and the size of an available area not assigned as a segment tothe external system.

[0383] [Write Command]

[0384] Parameters for the write command include the identificationnumber, the disk start address and the write size. The identificationnumber corresponds to the segment number set by the segment settingcommand. In the case under consideration, the identification number isassumed to be M where M=1 to N. The disk start address corresponds tothe write start address on the disk, and the write size corresponds tothe size of the data written, each being set in terms of sectors.

[0385] Upon application of a write command to the CPU 42 from theexternal system, the CPU 42 acquires the identification number M fromthe parameters of the input command, and reads the value set in thesegment setting register REG#M.

[0386] Then, the CPU 42 controls the host interface circuit 51 and thebuffer control circuit 53 thereby executing the processing of the hosttransfer in which data are transferred from the external system to thesegment #M. Concurrently with the host transfer processing, the CPU 42controls the buffer control circuit 53, the read/write signal processingcircuit 44 and the actuator drive circuit 48 thereby to execute the disktransfer processing in which data are transferred from the segment #M tothe disk 41.

[0387]FIG. 31 is a diagram showing parameters associated with theaccumulation of the segment #M, the host transfer and the disk transfer.The parameters for the segment #M, the host transfer processing and thedisk transfer processing are defined as follows.

[0388] Specifically, the segment size is defined as MSM, the segmentaccumulation amount as MAM, the available segment size as MFM, the writesize as MW, the read size as MR, the remaining host transfer data amountas MDH and the remaining disk transfer data amount as MDD (in units ofbytes). Also, the disk transfer rate is defined as VD (in units ofMB/s).

[0389] Now, the process of a host transfer for processing the writecommand will be explained in detail with reference to FIG. 32. The hosttransfer from the external system to the segment #M is executed whilemonitoring the available segment size MFM of the segment #M based on thehost transfer block size MBHM set in REG#M.

[0390]FIG. 32 is a flowchart showing the processing of host transferfrom the external system to the segment #M.

[0391] As shown in FIG. 32, with the activation of the host transferprocessing, the CPU 42 acquires the available size MFM of the segment #Mfrom the buffer control circuit 53 (step S191), and sets the hosttransfer size MTH (step S192). The host transfer size is the minimumvalue of the host transfer block size (MBHM

512) or the minimum value of the remaining host transfer data amountMDH.

[0392] Then, the CPU 42 compares the available segment size MFM with thehost transfer size MTH (step S193), and repeats this process until theavailable segment size reaches or exceeds the host transfer size (S191to S193). When the available segment size reaches or exceeds the hosttransfer size, a transfer ready signal is output to the external system(step S194), and the data equivalent to the host transfer size MTH inputfrom the external system is written in the segment (step S195).

[0393] After complete process of writing in the segment, the CPU 42calculates the remaining host transfer data amount (step S196) andchecks whether the remaining host transfer data is zero or not (stepS197). In the case where the remaining host transfer data amount islarger than zero, the host transfer process is repeatedly executed. Inthe case where the remaining host transfer data amount is zero, the hosttransfer process is terminated.

[0394] Now, the disk transfer processing in which data are transferredfrom the segment #M to the disk 41 will be explained with reference tothe flowchart of FIG. 33. The disk transfer in which data aretransferred to the disk 41 is executed while monitoring the segmentaccumulation amount MAM of the segment #M and the disk transfer forother segments based on the disk transfer block size MBDM set in theREG#M and the disk transfer priority order PDM. FIG. 33 is a flowchartshowing the processing of disk transfer from the segment #M to the disk1.

[0395] As shown in FIG. 33, upon activation of the disk transferprocessing, the CPU 42 acquires the segment accumulation amount MAM ofthe segment #M from the buffer control circuit 53 (step S201), and setsthe disk transfer size MTD (step S202). The disk transfer size is theminimum value of the disk transfer block size (MBDM×512) or the minimumvalue of the remaining disk transfer data amount MDD.

[0396] Then, the CPU 42 compares the segment accumulation amount MAMwith the disk transfer size MTD (step S203), and repeats this processuntil the segment accumulation amount reaches or exceeds the disktransfer size (S201 to S203). When the segment accumulation amountreaches or exceeds the disk transfer size, the CPU 42 monitors the disktransfer of other segments (step S204) and checks whether the disktransfer, higher in priority than the disk transfer of the segment #M,is under execution (step S205). When such a disk transfer is underexecution, the above-mentioned process is repeated until the disktransfer higher in priority order is complete (S204 to S205). When nodisk transfer higher in priority order is under execution, on the otherhand, the processing for writing the data equivalent to the disktransfer size into the disk 41 is executed (step S206).

[0397] After complete process of writing in the disk, the CPU 42calculates the remaining disk transfer data amount MDD (step S207), andchecks whether the remaining disk transfer data amount is zero or not(step S208). When the remaining disk transfer data amount is larger thanzero, the disk transfer processing is executed repeatedly (S201 toS208). When the remaining disk transfer data amount is zero, the disktransfer processing is complete.

[0398] [Read Command]

[0399] Parameters for the read command include the identificationnumber, the disk start address and the read size.

[0400] Upon application of a read command from the external system tothe CPU 42, the CPU 42 acquires the identification number L from theparameters of the input command and reads each parameter set in thesegment setting register REG#L.

[0401] Then, the CPU 42 controls the buffer control circuit 53, theread/write signal processing circuit 44 and the actuator drive circuit48. Thus, the processing of a disk transfer is executed from the disk 41to the segment #L. Concurrently with the disk transfer processing, theCPU 42 executes the processing of the host transfer from the segment #Lto the external system by controlling the host interface circuit 51 andthe buffer control circuit 53.

[0402] The processing of a disk transfer from the disk 41 to the segment#L is executed while monitoring the available segment size MFL of thesegment #L and the disk transfer of other segments based on the disktransfer block size MBDL set in the REG#L and the disk transfer priorityorder PDL.

[0403]FIG. 34 is a flowchart showing the processing of the disk transferfrom the disk 41 to the segment #L.

[0404] As shown in FIG. 34, upon activation of the disk transferprocessing, the CPU 42 acquires the available segment size MFL of thesegment #L from the buffer control circuit 53 (step S211), and sets thedisk transfer size MTD (step S212). The disk transfer size is theminimum value of the disk transfer block size (MBDM=512) or the minimumvalue of the remaining disk transfer data amount MDD.

[0405] Then, the CPU 42 compares the available segment size MFL with thedisk transfer size MTD (step S213), and repeats this process until theavailable segment size reaches or exceeds the disk transfer size (S211to S23). When the available segment size reaches or exceeds the disktransfer size, the CPU 42 monitors the disk transfer of other segments(step S214) and checks whether a disk transfer higher in priority orderthan the disk transfer of the segment #L is under execution (step S215).If such a disk transfer is under execution, the above-mentioned processis repeated until the disk transfer higher in priority order is complete(steps S214 to S215). In the case where no disk transfer higher inpriority order is under execution, on the other hand, the processing isexecuted for reading the data equivalent to the disk transfer size fromthe disk 41 (step S216).

[0406] Upon complete processing for reading the disk, the CPU 42calculates the remaining disk transfer data amount (step S217), andchecks whether the remaining disk transfer amount is zero or not (stepS218). In the case where the remaining disk transfer amount is largerthan zero, the disk transfer processing is repeatedly executed (stepsS211 to S218). In the case where the remaining disk transfer data amountis zero, in contrast, the disk transfer processing is completed.

[0407] Next, the processing of host transfer from the segment #L to theexternal system will be explained with reference to FIG. 35. FIG. 35 isa flowchart showing the processing of host transfer from the segment #Lto the external system.

[0408] The processing of the host transfer from the segment #L to theexternal system is executed while monitoring the segment accumulationamount of the segment #L based on the host transfer block size MBHL setin the register REG#L.

[0409] As shown in FIG. 35, upon activation of the host transferprocessing, the CPU 42 acquires the segment accumulation amount MAL ofthe segment #L from the buffer control circuit 53 (step S221) and setsthe host transfer size MTH (step S222). The host transfer size is theminimum value of the host transfer block size (MBHM

512) or the minimum value of the remaining host transfer data amountMDH.

[0410] Then, the CPU 42 compares the segment accumulation amount MALwith the host transfer size MTH (step S223), and repeats this processuntil the segment accumulation amount reaches or exceeds the hosttransfer size (S221 to S223). When the segment accumulation amountreaches or exceeds the host transfer size, the CPU 42 outputs a transferready signal to the external system (step S224), and the processing isexecuted for reading from the segment the data equivalent to the hosttransfer size MTH input from the external system (step S225).

[0411] After complete segment read processing, the CPU 42 calculates theremaining host transfer data amount (step S226), and checks whether theremaining host transfer data amount is zero or not (step S227). When theremaining host transfer data amount is larger than zero, the CPU 42repeatedly executes the host transfer processing. When the remaininghost data amount is zero, on the other hand, the host transferprocessing is terminated.

[0412] As described above, according to the seventh embodiment, theexternal system can set the segment size, the transfer block size andthe conditions for starting or stopping the transfer in the order ofpriority of the disk transfer size corresponding to each channel ofmulti-channel data into the disk apparatus by use of the segment settingcommand and the segment state request command in advance of therecording/reproducing operation.

[0413] A write command or a read command carrying an identificationnumber corresponding to each channel of multi-channel data is issuedduring the recording or reproduction. In this way, the disk apparatusaccording to the seventh embodiment can record or reproduce, each datain accordance with the segment size, the transfer block size and thedisk transfer priority order thus set.

[0414] As described above, in the disk apparatus according to theseventh embodiment, the segment size, the transfer block size and thedisk transfer priority order are set by segment based on the segmentsetting command from the external system, and the host transferprocessing and the disk transfer processing are controlled by a presetcontrol method. In this way, the memory size and the control methodcorresponding to each channel can be set at the time of multi-channelrecording and reproduction operation.

[0415] According to the seventh embodiment, a segment is set by thesegment setting command. The storage apparatus according to the presentinvention, however, can alternatively be configured in such a mannerthat the write data with the segment setting information attachedthereto is transferred to the disk apparatus, and the disk apparatusdetects the segment setting information contained in the write data orread data thereby to set a segment.

[0416] According to the seventh embodiment, the priority order of disktransfer, the disk transfer block size and the host transfer block sizeare determined as the transfer-starting conditions set for each segment.The storage apparatus according to the present invention, however, canalternatively be configured in such a manner as to control the start andstop of the disk transfer and the host transfer using or adding otherparameters.

[0417] According to the seventh embodiment, each segment is set byexecuting the segment setting command by segment. The storage apparatusaccording to the present invention, however, can alternatively beconfigured in such a manner as to provide a segment-setting command forsetting all the segments collectively.

[0418] According to the seventh embodiment, the identificationinformation of each command is set as a parameter of each command. Thestorage apparatus according to the seventh embodiment, however, canalternatively be configured in such a manner as to provide a dedicatedinformation setting command executed before issue of a writecommand/read command.

[0419] <<Embodiment 8>>

[0420] Now, a disk apparatus according to an eighth embodiment of thepresent invention will be explained. The configuration of the diskapparatus according to the eighth embodiment is substantially similar tothat of the disk apparatuses shown in FIGS. 26, 27 and 28. The diskapparatus according to the eighth embodiment processes a command forsetting the data transfer rate.

[0421] Explanation will be made about the operation of processing thetransfer rate setting command for the disk apparatus according to theeighth embodiment.

[0422] Parameters for the transfer rate setting command includes theidentification number, the access type and the transfer rate. Thetransfer rate, VCH, is the one guaranteed for the recording andreproduction of a corresponding channel data, and expressed in units ofsectors per second.

[0423]FIG. 36 is a flowchart showing the operation of processing thetransfer rate setting command according to the eighth embodiment.

[0424] As shown in FIG. 36, upon application of a transfer rate settingcommand from the external system to the CPU 42, the CPU 42 acquires eachset value from the parameters of the input command (step S231). Thevalues of the access type, the segment size, the disk transfer priorityorder, the disk transfer block size and the host transfer block size areset for each segment in the segment setting register 61 from the setaccess type, the transfer rate and the performance values (step S232).The set values including the available segment size are checked (stepS233). In the case where a set value is incorrect, an error message istransmitted to the external system (step S234). In the case where theset value is correct, the segment start addresses of REG#(K+1) to REG#Nare recalculated and set in each register (step S235), thus setting eachset value in REG#K (step S236).

[0425] For the data transfer rate to be guaranteed, it is necessary toset the disk transfer block size and the segment size correctly. Asetting method according to the eighth embodiment will be describedbelow.

[0426] According to the eighth embodiment, the performance values of theaccess performance and the disk transfer performance of the diskapparatus are expressed by the following parameters. Specifically, themaximum seek time is defined as TFS, the maximum rotational latency timeas TR (in units of ms), the channel setting rate as VCH and the disktransfer rate as VD (in sectors per second).

[0427] The maximum storage time TRW (in units of seconds) required forrecording the disk transfer block size MBDK (in units of sectors) in thedisk 41 or for reproducing it from the disk 41 is given as the sum ofthe maximum access time and the data transfer time, and expressed byequation (32) below.

TRW=TFS+TR+MBDK/VD   (32)

[0428] Thus the worst value VRW (in sectors per second) of the averagedisk transfer rate including the access time is calculated from equation(33).

VRW=MBDK/(TFS+TR+MBDK/VD)   (33)

[0429] If MBDK is set to secure the relation VCH

VRW for a set channel transfer rate VCH, the transfer at a rate not lessthan the channel transfer rate VCH can be guaranteed. Thus, equation(34) is derived from equations (32) and (33).

MBDK VCH×(TFS+TR)/(1−VCH/VD)   (34)

[0430] The disk transfer block size MBDK satisfies equation (34) and isset to the minimum integral multiple of eight sectors (4 kB). Otherparameters including the segment size MSK, the host transfer block sizeMBHK and the priority order of disk transfer are set by the settingmethod described below.

[0431] The segment size MSK (in units of sectors) is set to a minimumintegral multiple of eight sectors (4 kB) within a range meeting therelation MSK 2×MBDK and not exceeding the size of the available area.

[0432] The host transfer block size MBHK (in units of sectors), on theother hand, is set equal to MSK.

[0433] The priority order of disk transfer is set in the descendingorder of the channel transfer rate. For the same transfer rate, a higherpriority is set to the segment of access type called “write”.

[0434] Explanation will be made about an example of determining asegment set value specifically by the above-mentioned setting method:

VD=14000(sectors per second), TFS=0.02(seconds), TR=0.01(seconds)

[0435] With the number of channels as four, the transfer rate for eachchannel is set in the following manner:

VCH1=1000(sectors per second), VCH2=2000(sectors per second),VCH3=1400(sectors per second),and VCH4=2400(sectors per second).

[0436] In the process, the following calculations are made by equation(34) (figures below the decimal point rounded-up):

MBD1 1000×(0.02+0.01)/(1−1000/14000)=33

MBD2 2000×(0.02+0.01)/(1−2000/14000)=70

MBD3 1400×(0.02+0.01)/(1−1400/14000)=47

MBD4 2400×(0.02+0.01)/(1−2400/14000)=87

[0437] From these equations, each parameter can be calculated.

[0438] Disk transfer block size MBDK (K=1 to 4):

MBD1=40(sectors), MBD2=72(sectors),

MBD3=48(sectors), MBD4=88(sectors)

[0439] Segment size MSK (K=1 to 4):

MS1=80(sectors), MS2=144(sectors)

MS3=96(sectors), MS4=176(sectors)

[0440] Host transfer block size MBHK (K=1 to 4):

MBH1=80(sectors), MBH2=144(sectors)

MBH3=96(sectors), MBH4=176(sectors)

[0441] Disk transfer priority order PDK (K=1 to 4):

PD1=4, PD2=2, PD3=3, PD4=1

[0442] As described above, the external system sets the transfer rate ofeach channel in the disk apparatus. As a result, the disk apparatusaccording to the eighth embodiment can calculate and set the disktransfer block size required for guaranteeing the transfer rate on thebasis of the seek performance and the disk transfer rate of theapparatus.

[0443] In this way, the disk apparatus according to the eighthembodiment can guarantee the required data transfer rate by setting thesegment size and the transfer method for each segment on the basis ofthe data transfer rate of each channel supplied from the externalsystem.

[0444] According to the eighth embodiment, each segment is set by thetransfer rate setting command. The storage apparatus according to thepresent invention, however can alternatively be configured in such amanner that the data with write data transfer setting informationattached thereto is transferred to the disk apparatus, which in turndetects the transfer rate setting information included in the writedata/read data to set a segment.

[0445] According to the eighth embodiment, the priority order of disktransfer, the disk transfer block size and the host transfer block sizeare set as the transfer starting conditions set by segment. The storageapparatus according to the present invention, however, can alternativelybe configured in such a manner as to control the start and stop of disktransfer and the host transfer by using or adding another parameter.

[0446] According to the eight embodiment, the transfer rate itself isset as the transfer rate information from an external system. Thestorage apparatus according to the present invention, however, canalternatively be configured in such a manner as to set the image dataformat information as related to a preset speed type number and a presettransfer rate.

[0447] The eighth embodiment shows an example in which each set value ofthe segment setting register is determined from the transfer rateinformation. The setting method for the storage apparatus according tothe present invention, however, is not limited to such a method.

[0448] According to the eighth embodiment, the setting command can beexecuted by segment thereby to set each segment. The storage apparatusaccording to the present invention, however, can alternatively beconfigured to include setting commands for setting all the segmentscollectively.

[0449] According to the eighth embodiment, the identificationinformation for each command is set in the parameters of the particularcommand. The storage apparatus according to the present invention,however, can alternatively be configured in such a manner as to includea dedicated identification information setting command executed beforeissue of a write command/read command.

[0450] <<Embodiment 9>>

[0451] Now, explanation will be made about a disk apparatus according toa ninth embodiment of the present invention. The configuration of thedisk apparatus according to the ninth embodiment is substantiallysimilar to that of the disk apparatuses shown in FIGS. 26 and 27 exceptfor the segment setting register of the buffer control circuit 53.

[0452]FIG. 37 is a diagram showing the correspondence between thesegmentation of the buffer RAM 43 and the segment setting register 61 aaccording to the ninth embodiment.

[0453] As shown in FIG. 37, the segment setting register 61 a accordingto the ninth embodiment can set the access unit ACK making up a unit ofdata transfer from the external system. Thus, data can be written intoor read from the segment by the access unit ACK set by the segmentsetting register 61 a. This access unit ACK is given in bytes andselected from the values of power of 2 not more than 512.

[0454] The operation of processing the commands for the disk apparatusaccording to the ninth embodiment of the present invention will bedescribed below.

[0455] [Segment Setting Command]

[0456] Parameters of the segment setting command include the segmentnumber, the access type, the access unit, the segment size and thepriority order of disk transfer. The segment designated in the caseunder consideration is K.

[0457] Upon application of a segment setting command from the externalsystem to the CPU 42, the CPU 42 checks the parameters and thenrecalculates and sets the segment start address of each segment in theregister thereby to set other values in REG#K.

[0458] [Write Command/Read Command]

[0459] The write command and the read command are similar to thosedescribed above in the first embodiment. The start address, the writesize and the read size are set in units of sector.

[0460] [Segment Write Command]

[0461] Parameters of the segment write command include theidentification number, the segment address and the write size. Theidentification number corresponds to the segment number set by thesegment setting command. Let the identification number be K (K=1 to N).The segment address is the write address in the segment, and is set withthe start address of the segment as zero using the access unit set bythe segment setting command as a unit. The write size is also set usingthe access unit set by the segment setting command as a unit.

[0462] Upon application of a segment write command from an externalsystem to the CPU 42, the CPU 42 causes the execution of the hosttransfer from an external system to the segment #K in accordance withthe set segment size and the set write size.

[0463] Further, the CPU 42 calculates the write destination address(DA+SA) on the disk 41 from the start address DA (in units of sectors)on the disk set by the latest write command or the latest read commandexecuted for the segment #M and from the sector address SA (in unit ofsectors, with the first sector as zero) of the sector to be written inthe segment #K. The CPU 42 then executes the disk transfer fortransferring the updated data to the disk 41 in accordance with the setorder of disk transfer.

[0464] [Segment Read Command]

[0465] Parameters of the segment read command include the identificationnumber, the segment address and the read size. The segment address andthe read size are set in the access unit set by the segment settingcommand.

[0466] Upon application of a segment read command from the externalsystem to the CPU 42, the CPU 42 executes the host transfer from thesegment #M to the external system in accordance with the set segmentaddress and the set write size.

[0467] Now, explanation will be made about a method of using thiscommand.

[0468] First, the external system issues a segment setting command andsets the segment setting register 61 a as shown in FIG. 37. For thesegment #K to which access is desired, in units of words, the accesstype CSN is set to 3 (both for read and write operation) and the accessunit ACK is set to 2.

[0469] Then, the segment #K is designated to execute the write commandor the read command, so that the write data or the read data, as thecase may be, is set in the segment #K. After that, the data stored inthe segment #K is read by issuing a segment read command, and the storeddata is changed by issuing a segment write command. The data written inthe segment #K by the segment write command is written in thecorresponding area on the disk 41 by the processing in the diskapparatus, thus securing an identity between the data in the segment #Kand the data on the disk.

[0470] The segment #K thus set has stored therein, by reading with aread command, information such as the FAT (file allocation table)information which is frequently accessed and frequently rewritten insmall units. As a result, subsequent random access, in units of words,to the buffer memory becomes possible. At the same time, the wait timedue to disk access is eliminated, thereby improving the rewriteprocessing rate.

[0471] As described above, the disk apparatus according to the ninthembodiment permits the external system to directly randomly access thesegments of the buffer RAM of the disk apparatus with the access unitset as above. As a result, the disk apparatus according to the ninthembodiment can improve the random access efficiency.

[0472] According to the ninth embodiment, the segment is set by thesegment setting command. The storage apparatus according to the presentinvention, however, can alternatively be configured in such a mannerthat the write data, with the segment setting information attachedthereto, is transferred to the disk apparatus, which sets the segment bydetecting the segment setting information included in the writedata/read data.

[0473] The segment setting register according to the ninth embodiment isso configured as to set neither the disk transfer block size nor thehost transfer block size. The storage apparatus according to the presentinvention, however, can alternatively be configured in such a mannerthat such set values are added to the above-mentioned set values.

[0474] According to the ninth embodiment, each segment is set byexecuting the segment setting command for each segment. The storageapparatus according to the present invention, however, can alternativelybe configured in such a manner as to include a segment setting commandfor setting all the segments collectively.

[0475] According to the ninth embodiment, the identification informationof each command is set the parameters of each command. The storageapparatus according to the present invention, however, can alternativelybe configured to provide a dedicated identification information settingcommand executed before the write command/write command.

[0476] <<Embodiment 10>>

[0477] Now, explanation will be made about a disk apparatus according toa tenth embodiment of the present invention. The configuration of thedisk apparatus according to the tenth embodiment is substantiallysimilar to that of the disk apparatuses shown in FIGS. 26 and 27 exceptfor the segment setting register of the buffer control circuit 53.

[0478]FIG. 38 is a diagram showing the correspondence between thesegment setting register 61 b of the buffer control circuit 53, thesegmentation of the buffer RAM 43 and each area on the disk 41.

[0479] As shown in FIG. 38, the segment setting register 61 b has settherein the access type, the segment start address, the segment size,the disk start address, the disk area size and the access unit.According to each set value, segment #1 of the buffer RAM 43 correspondsto area 1 on the disk 41, segment #2 corresponds to area 2 on the disk2, and segment #K corresponds to area K on the disk 41. Also, it ispossible to set the access unit ACK providing a unit of data transferfrom the external system, and the operation of writing or reading datainto or from the disk apparatus can be performed in the access unit ACKthus set. The access unit ACK is given in bytes and selected from apower of 2 not more than 512. In the case under consideration, theaccess unit for the segment #K is 256 bytes.

[0480] Explanation will be made about the operation of processing thecommands for the disk apparatus according to the tenth embodiment.

[0481] [Segment Setting Command]

[0482] Parameters of the segment setting command include the segmentnumber, the access type, the disk start address, the disk area size, theaccess unit and the segment size. Assume that a segment number K isdesignated. The disk start address and the disk area size designate therange of the areas on the disk 41 in units of sectors, and this range ofareas is associated with the segment #K.

[0483] [Write Command]

[0484] Parameters of the write command include the identificationnumber, the write address and the write size. The identification numbercorresponds to the segment number set by the segment setting command.Assume that the identification number is K. The write address and thewrite size are set in the access unit set by the segment settingcommand. The write address is a write destination address with an areastart address of zero in the above-mentioned access unit within the areaK on the disk.

[0485] Upon application of a write command from the external system tothe CPU 42, the CPU 42 executes the host transfer from the externalsystem to the segment #K. Further, the CPU 42 calculates a writedestination address (DA+DW) on the disk 41 from the write address DW andthe start address DA of the area K on the disk 41 set by the segmentsetting register. Then, the CPU 42 executes the disk transfer fortransferring data to the disk 41.

[0486] [Read Command]

[0487] Parameters of the read command include the identification number,the read address and the read size. The read address and the read sizeare set in the access unit set by the segment setting command. The readaddress is a read destination address expressed in the above-mentionedaccess unit within the area K on the disk, and the area start address isassumed to be zero.

[0488] Upon application of a read command from the external systemthereto, the CPU 42 calculates the read destination address (DA+DR) onthe disk 41 from the read address DR and the start address DA on thedisk 41 set by the segment setting register, and executes the disktransfer for transferring the data from the disk 41 to the segment #K.Further, the CPU 42 executes the host transfer from the segment #K tothe external system.

[0489] As described above, the external system can set the access unitsfor access to different storage areas on the disk for each segment bythe segment setting command in the disk apparatus. The external systemcan also issue a write command or a read command for a segmentdesignated by the identification number, and can thus record orreproduce data in different areas on the disk by different access units.

[0490] As described above, the disk apparatus according to the tenthembodiment, different storage areas are set for different segments basedon the setting information supplied from the external system. In thisway, the storage areas and the segments can establish a one-to-onecorrespondence, thus easily guaranteeing the identity between the datain each segment and the data on the disk.

[0491] The access unit providing the size of the data transferredbetween the external system and the disk apparatus can be setindividually, and therefore can be set according to the type of the datato be recorded or to be reproduced.

[0492] The segment setting register according to the tenth embodiment isconfigured in a way not to set the disk transfer block size or the hosttransfer block size. The storage apparatus according to the presentinvention, however, can alternatively be configured to add these setvalues to other set values.

[0493] According to the tenth embodiment, the identification informationof each command is set in the parameters of each command. The storageapparatus according to the tenth embodiment, however, can alternativelybe configured in such a manner as to set a dedicated identificationinformation setting command executed before the write command/readcommand is issued.

[0494] According to the tenth embodiment, each segment is set byexecuting the segment setting command. The storage apparatus accordingto the present invention, however, can alternatively be configured insuch a manner as to provide a segment setting command for setting allthe segments collectively.

[0495] According to the tenth embodiment, a segment is set by thesegment setting command. The storage apparatus according to the presentinvention, however, can alternatively be configured in such a mannerthat the segment setting information is added to the write data andtransferred to the disk apparatus, which in turn detects the segmentsetting information included in the write data/read data thereby to seta segment.

[0496] Although the present invention has been described in terms of thepresently preferred embodiments, it is to be understood that suchdisclosure is not to be interpreted as limiting. Various alterations andmodifications will no doubt become apparent to those skilled in the artto which the present invention pertains, after having read the abovedisclosure. Accordingly, it is intended that the appended claims beinterpreted as covering all alterations and modifications as fall withinthe true spirit and scope of the invention.

I/we claim:
 1. In an I/O control apparatus comprising a temporary memorycircuit divisible into a plurality of segments according to the type ofan I/O request for temporarily storing data to and from an externalsystem and a notification means for notifying the external system of theamount of the data that can be transferred continuously between saidexternal system and said temporary memory circuit in response to a datatransfer amount request from said external system, an I/O control methodcomprising the steps of: selecting a data transfer method between saidexternal system and said storage apparatus in accordance with saidamount of the data that can be transferred continuously; selecting thenumber of data blocks that can be transferred continuously based on saidamount of the data that can be transferred continuously; and controllingthe transfer of the data I/O to and from said storage apparatus.
 2. TheI/O control method according to claim 1, comprising the steps of:reading periodically the amount of the data that can be transferredcontinuously; segmenting the data to be transferred into transfer datablocks each having not more than said amount of the data that can betransferred continuously; and controlling the input and the output ofsaid segmented transfer data blocks.
 3. A storage apparatus comprising:a temporary memory circuit divisible into a plurality of segmentsaccording to the type of an I/O request and for temporarily storing datato and from an external system; and a preread means for reading datafrom a designated area of a recording medium and storing the data onlytemporarily in a corresponding segment, wherein the size of thecorresponding available segment is given as a data size that can bepreread in response to a preread size request, and the size of the dataof a segment that has been preread in response to a read size request isgiven as a readable data size.
 4. A storage apparatus comprising: amanagement information memory means for storing file managementinformation corresponding to a position of data recorded in a recordingmedium; a temporary memory circuit divisible into a plurality ofsegments according to the type of an I/O request and capable of storingthe data temporarily to and from an external system; and a controlcircuit for: (1) reproducing said management information in response toan auto read request from the external system, (2) determining theposition of a block of said data on said recording medium for recordingsaid data block in said temporary memory for transfer to said externalsystem, and (3) prereading said data block.
 5. A storage apparatusaccording to claim 4, wherein said management information memory meansstores at least a data block number and the recording positioninformation of the data corresponding to said data block number, andwherein said control circuit receives said data block number from theexternal system at the time of receiving the auto read request from theexternal system, and selects the recording position informationcorresponding to said data block number from among the file managementinformation.
 6. A storage apparatus comprising: a temporary memorycircuit divisible into a plurality of segments according to the type ofan I/O request and for storing data temporarily to and from an externalsystem; a prefetch means for transferring the data reproduced from arecording medium to said temporary memory circuit; and a control circuitfor discriminating between the different types of an I/O request fromthe external system, and for selecting and executing a prefetch methodcorresponding to the type of said I/O request from among a plurality ofprefetch methods, the type of I/O request selecting one of differentdata amounts to be prefetched and different time lengths required forthe prefetching process.
 7. A storage apparatus comprising: a temporarymemory circuit divisible into a plurality of segments according to thetype of an I/O request and for storing data temporarily to and from anexternal system; a preread means for reproducing a data block from arecording medium and transferring said data block to said temporarymemory circuit; and a control circuit for receiving the I/O request withan identifier attached thereto from said external system and selectingand transferring to said external system a data block to be transferredto said external system, from among a plurality of said data blockspreread in accordance with said identifier.
 8. A storage apparatuscomprising: a temporary memory circuit divisible into a plurality ofsegments according to the type of an I/O request and for storing datatemporarily to and from an external system; and a control circuit fortemporarily storing the data from said external system in said temporarymemory in response to a write data request from said external system,determining the type of said write data request, and selecting theamount of the data to be recorded continuously in a recording medium inaccordance with the type thus determined.
 9. A storage apparatuscomprising: a temporary memory circuit divisible into a plurality ofsegments according to the type of an I/O request and for storing datatemporarily to and from an external system; an accumulation means foraccumulating read data requests from the external system; and a controlcircuit for determining the type of the read data requests received fromsaid external system, selecting and accumulating the read data requestsin accordance with the type of read data requests, and continuouslyreproducing the data from a recording medium in response to theaccumulated requests.
 10. A storage apparatus comprising: a temporarymemory circuit divisible into a plurality of segments according to thetype of an I/O request and for storing data temporarily to and from anexternal system; an accumulation means for accumulating I/O requestsfrom the external system; and a control circuit for determining the typeof the I/O requests accumulated, and selecting and executing the type ofthe I/O request to be processed in priority in accordance with theremaining time before a deadline calculated based on a limit time whensaid I/O request has attached thereto said time limit.
 11. A storageapparatus according to claim 10, further comprising: a detection meansfor detecting a continuously storable data amount in said temporarymemory circuit received from said external system as a data amount thatcan be transferred; and a control circuit for selecting as a request tobe executed an I/O request with a minimum remaining time before apredetermined deadline calculated based on a time limit from among theI/O requests with a time limit accumulated in said accumulation means,and extending said time limit of said request to be executed inaccordance with a possible delay time calculated in accordance with saiddata amount that can be transferred.
 12. A storage apparatus comprising:a temporary memory circuit divisible into a plurality of segmentsaccording to the type of an I/O request and for storing data temporarilyto and from an external system; and a control circuit including meansfor accumulating said I/O requests, means for calculating the timeremaining before a deadline based on a time limit of the accumulated I/Orequests, means for selecting an I/O request with a minimum remainingtime among said accumulated I/O requests, and means for executing saidI/O request when said minimum remaining time is smaller than apredetermined value and for executing in a selected order theaccumulated I/O requests in accordance with the recording position ofthe data corresponding to each of said I/O requests when theabove-mentioned conditions are not met.
 13. A storage apparatuscomprising: a temporary memory circuit divisible into a plurality ofsegments according to the type of an I/O request and for storing datatemporarily to and from an external system; a temporary memory circuitcontrol means for selecting said segments based on identificationinformation within a write request from the external system, temporarilystoring in said segments the data input from said external system insaid selected segments, and outputting said data as write data; and awrite means for writing said write data in a recording medium.
 14. Astorage apparatus comprising: a temporary memory circuit divisible intoa plurality of segments according to the type of an I/O request and forstoring data temporarily to and from an external system; a read meansfor reading data from a recording medium; and a temporary memory circuitcontrol means for selecting said segments based on identificationinformation within a read request from said external system, temporarilystoring the data read from said recording medium in said selectedsegments, and outputting said data to said external system.
 15. Astorage apparatus comprising: a temporary memory circuit divisible intoa plurality of segments according to the type of an I/O request and forstoring data temporarily to and from an external system; a segmentsetting means for setting at least one segment size, for transferringdata from the external system and for transferring write data to arecording medium, based on setting information supplied from saidexternal system; and a temporary memory circuit control means forselecting one of said segments based on identification informationwithin a write request from said external system, temporarily storingthe data input from said external system in said selected segment, andoutputting said data as write data; and a write means for writing saidwrite data into said recording medium.
 16. A storage apparatuscomprising: a temporary memory circuit divisible into a plurality ofsegments according to the type of an I/O request and for storing datatemporarily to and from an external system; a read means for readingdata from a recording medium; a segment setting means for setting atleast one segment size, for transferring data read from said recordingmedium and for transferring data to said external system for eachsegment based on setting information supplied from said external system;and a temporary memory circuit control means including means forselecting one of said segments based on identification informationwithin a read request from said external system, means for temporarilystoring in said selected segment the data read from said recordingmedium based on said transfer of said data, and means for outputtingsaid data to said external system.
 17. A storage apparatus according toclaim 15, wherein said segment setting means sets at least one conditionfor starting/stopping the data transfer to or from said external systemand the condition for starting/stopping the transfer of read data fromsaid recording medium for each segment is based on the settinginformation from said external system.
 18. A storage apparatus accordingto claim 16, wherein said segment setting means sets at least onecondition for starting/stopping the data transfer to or from saidexternal system for each segment and the condition for starting/stoppingthe transfer of write data to said recording medium is based on thesetting information from said external system.
 19. A storage apparatusaccording to claim 15, wherein said segment setting means is configuredin such a manner as to set the order of priority of the read datatransfer from said recording medium for each segment based on thesetting information supplied from the external system.
 20. A storageapparatus according to claim 16, wherein said segment setting means isconfigured in such a manner as to set the order of priority of the writedata transfer to said recording medium for each segment based on thesetting information supplied from the external system.
 21. A storageapparatus according to claim 15, wherein said segment setting means isconfigured in such a manner as to set at least one segment size, whereinthe data input from the external system for each segment and datatransferred to said recording medium for each segment, is based on thesetting information supplied from said external system.
 22. A storageapparatus according to claim 16, wherein said segment setting means isconfigured in such a manner as to set at least one segment size, whereinthe data output from said recording medium for each segment and datatransferred to said external system for each segment, is based on thedata setting information from said external system.
 23. A storageapparatus according to claim 15, wherein said segment setting means isconfigured in such a manner as to set an access unit constituting a unitof data transfer from said external system for each segment, based onthe setting information supplied from said external system.
 24. Astorage apparatus according to claim 16, wherein said segment settingmeans is configured in such a manner as to set an access unitconstituting a unit of data transfer to said external system for eachsegment, based on the setting information supplied from said externalsystem.
 25. A storage apparatus comprising: a temporary memory circuitdivisible into a plurality of segments according to the type of an I/Orequest and for storing data temporarily to and from an external system;an access unit setting means for setting an access unit constituting aunit of data transfer to or from the external system for each segment,based on setting information supplied from said external system; atemporary memory circuit control means for selecting said segment basedon identification information of a write request or a read request fromsaid external system and for writing or reading data into or from saidselected segment randomly in units of said access unit; and a write/readmeans for writing or reading data into or from said selected segment.26. A storage apparatus comprising: a temporary memory circuit divisibleinto a plurality of segments according to the type of an I/O request andfor storing data temporarily to and from an external system; arecording-reproducing area setting means for setting arecording-reproducing area of a recording medium for each segment basedon setting information supplied from the external system; a temporarymemory circuit control means for selecting one of said segments based onidentification information within a write request or a read request fromsaid external system, and temporarily storing in said selected segmentwrite data input from said external system or outputting data stored insaid temporary memory from said selected segment to said externalsystem; and a write/read means for writing data from said selectedsegment into said set recording-reproducing area or reading data fromsaid set recording-reproducing area into said selected segment.